rtl Architecture Reference

process fpga common slaves More...

Signals
ipbw	ipb_wbus_array ( N_SLAVES- 1 downto 0 )
ipbr	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
ipbr_d	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
ctrl_pulse_reg	std_logic_vector ( 63 downto 0 )
nc_0	std_logic_vector ( 63 downto 0 )
nc_1	std_logic_vector ( 63 downto 0 )
nc_2	std_logic_vector ( 63 downto 0 )
flash_spi_in	spi_mi
flash_spi_out	spi_mo
tob_delay_default	std_logic_vector ( 31 downto 0 )
tob_bc_default	std_logic_vector ( 31 downto 0 )

Instantiations
fabric	ipbus_fabric_sel
module_control	ipbus_ctrlreg_v
tob_synch	ipbus_ctrlreg_v
xadc	ipbus_xadc_drp <Entity ipbus_xadc_drp>
reconfig	ipbus_ctrlreg_v
ttc_orbit_length	ipbus_ctrlreg_v
bcmuxvalue_sync	ipbus_ctrlreg_v
tob_bus_delay	ipbus_ctrlreg_v
tob_bc_delay	ipbus_ctrlreg_v
spi_flash	ipbus_spi32 <Entity ipbus_spi32>
ram	ipbus_ram

Detailed Description

process fpga common slaves

This slave process_fpga comprises a collection of IPBus slaves of the process FPGAs a slave being an interface between IPBus and the application logic It implements a simple control or status register, an area of RAM that is mapped to IPBus, a stare machine under IPBus control, or an interface to a second bus, such as SPI and XADC. The ipbus bus fabric, address select logic, data multiplexers This version selects the addressed slave depending on the state of incoming control lines

Author

Mohammed Siyad

Definition at line 69 of file slave_process_fpga.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Process_Common_slave/slave_process_fpga.vhd