ipbus_spi32 Entity Reference

ipbus_spi32 More...

Inheritance diagram for ipbus_spi32:

Entities
rtl	architecture
	ipbus_spi32 More...

Libraries
IEEE
ipbus_lib

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
ipbus
spi	Package <spi>
ipbus_reg_types

Generics
BYTE_SPI	boolean := FALSE
ADDR_WIDTH	natural

Ports
ipbus_clk	in	std_logic
		ipbus clk of 31.25MHz
reset	in	std_logic
		reset
ipb_in	in	ipb_wbus
		IPBus input bus going from master to slaves.
ipb_out	out	ipb_rbus
		IPBus output bus going from slaves to master.
spi_in	in	spi_mi
		spi input signals
spi_out	out	spi_mo
		spi output signals
selreg	out	std_logic_vector ( 1 downto 0 )
		select output

Attributes
keep_hierarchy	string
keep_hierarchy	entity is " yes "

Detailed Description

ipbus_spi32

ipbus interface to SPI engine for FLASH memory and PLL chips on FTM /eFEX

Author

Richard Staley

Definition at line 17 of file ipbus_spi32.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_spi32.vhd