rtl Architecture Reference

ipbus_spi32 More...

Processes
clock_div	( reset , ipbus_clk )

Constants
DIV_BITS	natural := 2
NSLV	positive := 4

Signals
ram_ptr	std_logic_vector ( ADDR_WIDTH- 3 downto 0 )
ram_write	std_logic
outgoing_data	std_logic_vector ( 31 downto 0 )
incoming_data	std_logic_vector ( 31 downto 0 )
spi_clk	std_logic := ' 0 '
clk_en	std_logic := ' 0 '
ipbw	ipb_wbus_array ( NSLV- 1 downto 0 )
ipbr	ipb_rbus_array ( NSLV- 1 downto 0 )
ipbr_d	ipb_rbus_array ( NSLV- 1 downto 0 )
spi_ctrl	ipb_reg_v ( 3 downto 0 )
spi_stat	ipb_reg_v ( 0 downto 0 )
transfer_count	std_logic_vector ( ADDR_WIDTH downto 0 )
do_spi	std_logic
run_spi	std_logic
busy	std_logic

Instantiations
block_decode	ipbus_fabric_branch
spi_control	ipbus_ctrlreg_v
arbitration	ipbus_watchdog <Entity ipbus_watchdog>
spi_dpram_out	ipbus_dpram_flash <Entity ipbus_dpram_flash>
spi_dpram_in	ipbus_dpram_flash <Entity ipbus_dpram_flash>
synch	command_sync <Entity command_sync>
spi_engine	spi32_8_control <Entity spi32_8_control>
gen_clock	clock_pulse <Entity clock_pulse>

Detailed Description

ipbus_spi32

ipbus interface to SPI engine for FLASH memory and PLL chips on FTM /eFEX

Author

Richard Staley

Definition at line 47 of file ipbus_spi32.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_spi32.vhd