ipbus_dpram_flash Entity Reference

ipbus dpram flash More...

Inheritance diagram for ipbus_dpram_flash:

Entities
rtl	architecture
	ipbus dpram flash More...

Libraries
IEEE
ipbus_lib

Use Clauses
STD_LOGIC_1164
numeric_std
ipbus

Generics
ADDR_WIDTH	natural

Ports
clk	in	std_logic
		write clock
rst	in	std_logic
		reset
ipb_in	in	ipb_wbus
		IPBus input bus going from master to slaves.
ipb_out	out	ipb_rbus
		IPBus output bus going from slaves to master.
rclk	in	std_logic
		read clock
we	in	std_logic := ' 0 '
		write enable
d	in	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
		data in
q	out	std_logic_vector ( 31 downto 0 )
		data out
addr	in	std_logic_vector ( ADDR_WIDTH- 1 downto 0 )
		address

Detailed Description

ipbus dpram flash

Generic 32b wide dual-port memory with ipbus access on one port Should lead to an inferred block RAM in Xilinx parts with modern tools Added initialisation of RAM

Author

Richard Staley

Definition at line 16 of file ipbus_dpram_flash.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd