rtl Architecture Reference

ipbus dpram flash More...

Processes
PROCESS_66	( clk )
PROCESS_67	( rclk )

Types
ram_array	( 0 to 2 ** ADDR_WIDTH- 1 ) std_logic_vector ( 31 downto 0 )

Signals
sel	integer range 0 to 2 ** ADDR_WIDTH- 1 := 0
rsel	integer range 0 to 2 ** ADDR_WIDTH- 1 := 0
ack	std_logic

Shared Variables
ram	shared ram_array := := ( X " 03000000 " , others = > X " 00000000 " )

Detailed Description

ipbus dpram flash

Generic 32b wide dual-port memory with ipbus access on one port Should lead to an inferred block RAM in Xilinx parts with modern tools Added initialisation of RAM

Author

Richard Staley

Definition at line 44 of file ipbus_dpram_flash.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_dpram_flash.vhd