ipbus_dpram_flash.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library ipbus_lib;
use ipbus_lib.ipbus.all;
 
entity ipbus_dpram_flash is
    generic(
        ADDR_WIDTH: natural
    );
    port(
        clk: in std_logic;
        rst: in std_logic;
        ipb_in: in ipb_wbus;
        ipb_out: out ipb_rbus;
        rclk: in std_logic;
        we: in std_logic := '0';
        d: in std_logic_vector(31 downto 0) := (others => '0');
        q: out std_logic_vector(31 downto 0);
        addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0)
    );
    
end ipbus_dpram_flash;
 
architecture rtl of ipbus_dpram_flash is
 
    type ram_array is array(0 to 2 ** ADDR_WIDTH - 1 ) of std_logic_vector(31 downto 0);-- order reversed to allow initialisation from 0
    
    shared variable ram: ram_array :=(
--   X"9F000000",  others => X"00000000" ); -- read ID codes
   X"03000000",  others => X"00000000" ); -- read from address 0
    
    signal sel, rsel: integer range 0 to 2 ** ADDR_WIDTH - 1 := 0;
    signal ack: std_logic;
 
begin
 
    sel <= to_integer(unsigned(ipb_in.ipb_addr(ADDR_WIDTH - 1 downto 0)));
 
    process(clk)
    begin
        if rising_edge(clk) then
            ipb_out.ipb_rdata <= ram(sel); -- Order of statements is important to infer read-first RAM!
            if ipb_in.ipb_strobe='1' and ipb_in.ipb_write='1' then
                ram(sel) := ipb_in.ipb_wdata;
            end if;
            ack <= ipb_in.ipb_strobe and not ack;
        end if;
    end process;
    
    ipb_out.ipb_ack <= ack;
    ipb_out.ipb_err <= '0';
    
    rsel <= to_integer(unsigned(addr));
    
    process(rclk)
    begin
        if rising_edge(rclk) then
            q <= ram(rsel); -- Order of statements is important to infer read-first RAM!
            if we = '1' then
                ram(rsel) := d;
            end if;
        end if;
    end process;
 
end rtl;