clock_pulse Entity Reference

clcock pulse More...

Inheritance diagram for clock_pulse:

Entities
rtl	architecture
	clcock pulse More...

Libraries
ieee

Use Clauses
std_logic_1164

Ports
CLK_I	in	std_logic
		clock in
RESET	in	std_logic
		reset
Enable	in	std_logic
		enable
pulse	out	std_logic
		pulse created from the enable siganl

Detailed Description

clcock pulse

Tis module creates pulse It receives enable and clock in and creates pulse signal

Author

Richard Staley

Definition at line 12 of file clock_pulse.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Process_Common_slave/clock_pulse.vhd