rtl Architecture Reference

clcock pulse More...

Processes
PROCESS_64	( clk_i , reset , enable )
PROCESS_65	( clk_i , reset )

Signals
ClockR	std_logic := ' 0 '
ClockF	std_logic := ' 0 '

Detailed Description

clcock pulse

Tis module creates pulse It receives enable and clock in and creates pulse signal

Author

Richard Staley

Definition at line 26 of file clock_pulse.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Process_Common_slave/clock_pulse.vhd