spi32_8_control Entity Reference

icontroller for SPI interface PLL chips of FTM /eFEX More...

Inheritance diagram for spi32_8_control:

Entities
rtl	architecture
	icontroller for SPI interface PLL chips of FTM /eFEX More...

Libraries
IEEE

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned

Generics
ADDR_WIDTH	natural
BYTE_SPI	boolean := FALSE

Ports
spi_clk	in	std_logic
		spi clock
reset	in	std_logic
		reset
outgoing_data	in	std_logic_vector ( 31 downto 0 )
		data going to the spi flash
incoming_data	out	std_logic_vector ( 31 downto 0 )
		data from the spi flash
run_spi	in	std_logic
		run spi controller
busy	out	std_logic := ' 0 '
		busy
transfer_count	in	std_logic_vector ( ADDR_WIDTH+ 1 downto 0 )
		data transfer count
ram_ptr	out	std_logic_vector ( ADDR_WIDTH- 2 downto 0 )
		ram pointer
ram_write	out	std_logic := ' 0 '
		write enable of the ram
clk_en	out	std_logic := ' 0 '
		clock enable
cs_n	out	std_logic := ' 1 '
		chip select of the spi flssh
mosi	out	std_logic := ' 0 '
		mosi to spi flash
miso	in	std_logic := ' 0 '
		miso from spi flash

Detailed Description

icontroller for SPI interface PLL chips of FTM /eFEX

Buffer RAMs are 32 bits wide. The word at outgoing buffer(index) is read and a spi frame sent. Returning data is written into incoming buffer(index), the first word/byte can be discarded. Index' increments until 'transfer_count' words/bytes are transfered. Transfer count either in bytes or words, set by BYTE_SPI switch.

Author

Richard Staley

Definition at line 15 of file spi32_8_control.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Process_Common_slave/spi32_8_control.vhd