rtl Architecture Reference

icontroller for SPI interface PLL chips of FTM /eFEX More...

Processes
spi_sequencer	( spi_clk , reset , sequencer , run_spi , shift_count )
serdes	( spi_clk , shift_register )
chip_enable	( spi_clk , shift_register )
chip_enable	( spi_clk , shift_register )

Constants
MSB_FIRST	boolean := BYTE_SPI
BIG_FRAME	boolean := BYTE_SPI
TRAP_CODE	boolean := not BYTE_SPI
otp_code	std_logic_vector ( 31 downto 0 ) := x " 0000A03F "

Types
shiftstate	( idle , start_frame , read_mem , shift_io , write_mem , end_frame )

Signals
sequencer	shiftstate := idle
shift_count	integer range 0 to 32 := 0
shift_register	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
mosi_data	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
miso_rising	std_logic
le_int	std_logic := ' 0 '
ram_index_u	unsigned ( ADDR_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
num_words	std_logic_vector ( ADDR_WIDTH- 1 downto 0 )
num_32words	unsigned ( ADDR_WIDTH- 1 downto 0 )
ram_index_slv	std_logic_vector ( ADDR_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
term_le	std_logic := ' 0 '

Attributes
dont_touch	string
dont_touch	signal is " true "

Aliases
rem_bytes	transfer_count ( 1 downto 0 )

Detailed Description

icontroller for SPI interface PLL chips of FTM /eFEX

Buffer RAMs are 32 bits wide. The word at outgoing buffer(index) is read and a spi frame sent. Returning data is written into incoming buffer(index), the first word/byte can be discarded. Index' increments until 'transfer_count' words/bytes are transfered. Transfer count either in bytes or words, set by BYTE_SPI switch.

Author

Richard Staley

Definition at line 50 of file spi32_8_control.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Process_Common_slave/spi32_8_control.vhd