ipbus_watchdog Entity Reference

ipbus watchdog More...

Inheritance diagram for ipbus_watchdog:

Entities
rtl	architecture
	ipbus watchdog More...

Libraries
IEEE
ipbus_lib

Use Clauses
STD_LOGIC_1164
numeric_std
ipbus
ipbus_reg_types
watchdog	Package <watchdog>

Generics
TIMER_WIDTH	natural := 10

Ports
ipbus_clk	in	STD_LOGIC
		IPBus clock of 31.25MHz.
reset	in	STD_LOGIC
		reset
ipbus_in	in	ipb_wbus
		IPBus input bus going from master to slaves.
ipbus_out	out	ipb_rbus
		IPBus output bus going from slaves to master.

Detailed Description

ipbus watchdog

Ipbus Lock bit with Timer. Provides for indivisable access for IPBus slaves when used with Lock + Watchdog Timer aware software

Author

Richard Staley

Definition at line 19 of file ipbus_watchdog.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_watchdog.vhd