rtl Architecture Reference

ipbus watchdog More...

Processes
transitions	( ipbus_clk , lock , previous_lock )
key_op	( ipbus_clk , access_key , lock , previous_lock )
writeop	( ipbus_clk , addr , ipbus_in .ipb_wdata , ipbus_in .ipb_strobe , ipbus_in .ipb_write , ack )
timeout_flag	( ipbus_clk , timeout , lock , ipbus_in .ipb_wdata( 0 ) )
pulseop	( ipbus_clk , addr , ipbus_in .ipb_wdata , ipbus_in .ipb_strobe , ipbus_in .ipb_write )
ticker	( reset , ipbus_clk )
watchdog_timer	( ipbus_clk , tick1ms )

Constants
timer_padding	std_logic_vector ( 31 downto TIMER_WIDTH ) := ( others = > ' 0 ' )

Signals
addr	natural range 0 to 7
ack	std_logic := ' 0 '
timeout_value	std_logic_vector ( TIMER_WIDTH- 1 downto 0 ) := std_logic_vector ( to_unsigned ( DEFAULT_TIMEOUT , TIMER_WIDTH ) )
access_key	unsigned ( 29 downto 0 ) := ( others = > ' 0 ' )
lock	std_logic := ' 0 '
previous_lock	std_logic := ' 0 '
poslock	std_logic := ' 0 '
neglock	std_logic := ' 0 '
tick1ms	std_logic
wr_timer	std_logic := ' 0 '
wr_error	std_logic := ' 0 '
timer_running	std_logic := ' 0 '
previous_timer_running	std_logic := ' 0 '
timeout	std_logic := ' 0 '
t_error	std_logic := ' 0 '

Detailed Description

ipbus watchdog

Ipbus Lock bit with Timer. Provides for indivisable access for IPBus slaves when used with Lock + Watchdog Timer aware software

Author

Richard Staley

Definition at line 37 of file ipbus_watchdog.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Process_Common_slave/ipbus_watchdog.vhd