Top of the process FPGA.
This is the top level of the eFEX Processor firmware. The logic implemented here can be grouped into the areas of real-time, readout, control and infrastructure.
Real-Time Logic
This logic implements the core functionality of the eFEX. It forms part of the real-time L1 processing chain that forms the trigger decision. There are 4 Processor FPGAs on the eFEX, and not all of them implement the same real-time logic, as explained below.
Every Processor FPGA performs the following real-time functions:
- Receives 64 channels of serial data at 11.2 Gb/s.
- Transfers these data to the 40.08 MHz LHC clock domain, in the process aligning them to each other and the LHC clock, with a fixed latency.
- Transfers the aligned data to a 200 MHz clock domain and runs electro-magnetic (EM) and Tau feature-extraction algorithms, generating Trigger Objects (TOBs).
- Sorts the EM and Tau TOBs over the FPGA, in order of priority, in the process transfering them to the 280 MHz clock domain. Additionally, 1 Processor FPGAs on every eFEX also performs the following real-time functions.
- Receives EM TOBs from the other 3 Processor FPGAs and sorts them plus its own EM TOBs in order of priority.
- Transmits the 6 highest-priority EM TOBs per BC to Topo, at 11.2 Gb/s. And 1 Processor FPGAs on every eFEX also performs the following real-time functions.
- Receives Tau TOBs from the other 3 Processor FPGAs and sorts them plus its own Tau TOBs in order of priority.
- Transmits the 6 highest-priority Tau TOBs per BC to Topo, at 11.2 Gb/s. Those Processor FPGAs that do not perform this second stage of EM or Tau TOB sorting, transmit their TOBs (either EM or Tau or both) to those FPGAs that do. For each type, up to 6 TOBs are transmitted at 280 Mhz per BC. The real-time logic comprises the following blocks.
- data_path_block (top level of a block that includes data alignment, feature-extraction algorithms and FPGA-level TOB merging)
- IPBusTopMergingModule (module-level TOB merging, plus control interface to that logic. Not implemented in all versions of the Processor FPGA firmware; determined by the generic parameter FLAVOUR.)
- efex_topo_tx (formatting of TOB data for transmission to L1Topo) Readout Logic The readout logic of the Processor FPGA performs the following functions.
- For each BC, the input data, TOBs, and intermediate TOB data (xTOBs) are copied from the real-time logic and held in pipeline memories until the arrival (or not) of the L1A/L0A signal for that BC.
- If an L1A/L0A is received for a BC, some subset of the above data are transmitted downstream on the readout path to the Control FPGA, at 11.2 Gb/s. The subset transmitted depends on the slow-control settings and the current state of the buffer occupancy on the readout path. See the lower levels of the firmware and [ref to data format doc] for details. All of the readout logic is contained with the following block.
- Readout_logic_top (top level of all readout logic)
Control Interface
The control interface is implemented using IP from the IPBus project, which provides access to registers and RAM space within the firmware. For documentation on IPBus, see https://ipbus.web.cern.ch/introduction/ The control interface comprises the following modules.
- proc_FPGAs (IPBus, UDP slave interface to the Control FPGA)
- ipbus_fabric_sel (address-select logic plus data multiplexers)
- common_id_registers (ID registers)
- lib_registers (registers)
- slaves (IPBus-SPI interface to external components)
- startup (Xilinx IP that provides a user interface FPGA configuration and control signals)
- self_configure (FPGA re-configuration control)
- mgt_slaves (control interface of all MGTs)
Infrastructure
The following blocks implement resources that are used by many or all of the other areas of logic.
Example of timing diagram
┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐
CLK: ──┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─
┌───┐ ┌───┐ ┌─┐ ┌─────┐ ┌─┐ ┌─┐
SIG1: ──┘ └─┘ └─┘ └─┘ └───┘ └─┘ └
┌─────┐ ┌─┐ ┌─┐ ┌───┐
SIG2: ──┘ └───┘ └───┘ └───┘ └────
┬─────┬────┬────┬────┬────┬
Data: │ │ A1 │ A2 │ X │ │
┴─────┴────┴────┴────┴────┴- Author
- Mohammed Syiad
-
Francesco Gonnella
-
Saeed Taghavi
Definition in file top_efex_processor.vhd.
1.9.1