Behavioral Architecture Reference

Top of the process FPGA. More...

Processes
force_rx_error	( mac_clk )
PROCESS_72	( mac_clk )
clk_proc	( clk280 )
synch_L1A_in	( clk40 )
io_reg_0	( clk280 )
io_reg_1	( clk280 )
TOB_BCN_sync_proc	( clk280 )
proc_clk_280	( clk280 )
ila_clk_proc	( clk280 )

Components
io_delay
io_delay2

Signals
q_clk_gtrefclk_pad_n_in	std_logic_vector ( 19 downto 0 )
	mgts reference clocks
q_clk_gtrefclk_pad_p_in	std_logic_vector ( 19 downto 0 )
	mgts reference clocks
rxn_IN	std_logic_vector ( 79 downto 0 )
	mgt rx side inputs
rxp_IN	std_logic_vector ( 79 downto 0 )
	mgt rx side inputs
ttc_inform_p	std_logic_vector ( 3 downto 0 )
	ttc information that has L1A,BCR and ECR
ttc_inform_n	std_logic_vector ( 3 downto 0 )
	ttc information that has L1A,BCR and ECR
ttc_info	std_logic_vector ( 37 downto 0 )
	ttc information ECR ID and L1ID (Phase-I), L0ID (Phase-II)
ttc_parity	std_logic
	Odd parity over ttc ECRID and L1ID.
ctrl_TOB_ready_in	std_logic
	Ready signal from control FPGA to receive TOB data.
ctrl_RAW_ready_in	std_logic
	Ready signal from control FPGA to receive RAW calorimeter data.
data_from_fpga_A_p	std_logic_vector ( 32 downto 0 )
	merging data from another fpga
data_from_fpga_A_n	std_logic_vector ( 32 downto 0 )
	merging data from another fpga
data_from_fpga_B_p	std_logic_vector ( 32 downto 0 )
	merging data from another fpga
data_from_fpga_B_n	std_logic_vector ( 32 downto 0 )
	merging data from another fpga
data_from_fpga_C_p	std_logic_vector ( 32 downto 0 )
	merging data from another fpga
data_from_fpga_C_n	std_logic_vector ( 32 downto 0 )
	merging data from another fpga
txn_OUT	std_logic_vector ( 77 downto 0 )
	mgts tx side outputs
txp_OUT	std_logic_vector ( 77 downto 0 )
	mgts tx side outputs
data_to_fpga_X_p	std_logic_vector ( 32 downto 0 )
	merging data from this fpga to another fpga
data_to_fpga_X_n	std_logic_vector ( 32 downto 0 )
	merging data from this fpga to another fpga
data_to_fpga_Y_p	std_logic_vector ( 32 downto 0 )
	merging data from this fpga to another fpga
data_to_fpga_Y_n	std_logic_vector ( 32 downto 0 )
	merging data from this fpga to another fpga --
busy_raw	std_logic
	raw data busy out
busy_tob	std_logic
	tob data busy out
MGT_QUAD_ENABLE	std_logic_vector ( 19 downto 0 ) := x " fffff "
MGT_USE_OTHER_CLK	std_logic_vector ( 19 downto 0 ) := x " 00000 "
MGT_TX_POWER	std_logic_vector ( 79 downto 0 ) := ( others = > ' 1 ' )
MGT_RX_POWER	std_logic_vector ( 79 downto 0 ) := ( others = > ' 1 ' )
clk200	std_logic
clk_load	std_logic
ipb_clk	std_logic
mac_clk	std_logic
clk40	std_logic
clk40_rdout_i	std_logic
clk280	std_logic
clk280_90	std_logic
clk200_iodelay	std_logic
onehz	std_logic
ipb_rst	std_logic
rst_macclk	std_logic
rst_ipb	std_logic
start	std_logic
reset	std_logic
locked_40m_i	std_logic
algo_ipb_in	ipb_rbus
algo_ipb_out	ipb_wbus
ipbw	ipb_wbus_array ( N_SLAVES- 1 downto 0 )
ipbr	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
ipb_in	ipb_rbus
ipb_out	ipb_wbus
MGT_Commadet_int	std_logic_vector ( 79 downto 0 )
rxdata	std_logic_vector ( 79 downto 0 )
clk280_int	std_logic_vector ( 79 downto 0 )
flash_clk	std_logic
Module_ID	std_logic_vector ( 31 downto 0 )
fpga_id	std_logic_vector ( 31 downto 0 )
hw_position	std_logic_vector ( 31 downto 0 )
fw_rev	std_logic_vector ( 31 downto 0 )
fw_tag	std_logic_vector ( 31 downto 0 )
datafmt_rev	std_logic_vector ( 31 downto 0 )
status	std_logic_vector ( 31 downto 0 )
trigger_reconfig	std_logic
reconfig	std_logic
control_reg	std_logic_vector ( 31 downto 0 )
reconfig_reg	std_logic_vector ( 31 downto 0 )
master_rx_data_int	std_logic_vector ( 9 downto 0 )
master_tx_data_int	std_logic_vector ( 9 downto 0 )
master_tx_pause_int	std_logic
force_rx_error_buf	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
data_from_fpga_A	std_logic_vector ( 32 downto 0 )
data_from_fpga_B	std_logic_vector ( 32 downto 0 )
data_from_fpga_C	std_logic_vector ( 32 downto 0 )
eg_tob_0	std_logic_vector ( 31 downto 0 )
eg_tob_1	std_logic_vector ( 31 downto 0 )
eg_tob_2	std_logic_vector ( 31 downto 0 )
eg_tob_3	std_logic_vector ( 31 downto 0 )
eg_tob_4	std_logic_vector ( 31 downto 0 )
eg_tob_5	std_logic_vector ( 31 downto 0 )
eg_tob_6	std_logic_vector ( 31 downto 0 )
eg_tob_7	std_logic_vector ( 31 downto 0 )
OUT_tau_XTOB	AlgoXOutput
OUT_eg_XTOB	AlgoXOutput
sorted_tau_TOB	AlgoTriggerObject
sorted_eg_TOB	AlgoTriggerObject
OUT_eg_Sync	std_logic
OUT_tau_Sync	std_logic
OUT_eg_Valid	std_logic_vector ( OUTPUT_TOBS- 1 downto 0 )
OUT_tau_Valid	std_logic_vector ( OUTPUT_TOBS- 1 downto 0 )
sorted_eg_Valid	std_logic
sorted_tau_start	std_logic
sorted_eg_start	std_logic
tau_tob_0	std_logic_vector ( 31 downto 0 )
tau_tob_1	std_logic_vector ( 31 downto 0 )
tau_tob_2	std_logic_vector ( 31 downto 0 )
tau_tob_3	std_logic_vector ( 31 downto 0 )
tau_tob_4	std_logic_vector ( 31 downto 0 )
tau_tob_5	std_logic_vector ( 31 downto 0 )
tau_tob_6	std_logic_vector ( 31 downto 0 )
tau_tob_7	std_logic_vector ( 31 downto 0 )
data_merge_1	std_logic_vector ( 32 downto 0 )
data_merge_2	std_logic_vector ( 32 downto 0 )
data_merge_3	std_logic_vector ( 32 downto 0 )
data_merge_4	std_logic_vector ( 32 downto 0 )
data_merge_i	AlgoTriggerObjects ( 3 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
data_merge_ii	AlgoTriggerObjects ( 3 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
sorted_merged_Start	std_logic := ' 0 '
sorted_merged_Valid	std_logic := ' 0 '
sorted_merged_TOB	AlgoTriggerObject := ( others = > ' 0 ' )
MGT_CLK_GTREFCLK_PAD_N_IN	std_logic_vector ( 79 downto 0 )
MGT_CLK_GTREFCLK_PAD_P_IN	std_logic_vector ( 79 downto 0 )
mgt_RXUSRCLK_OUT	std_logic_vector ( 79 downto 0 )
rx_resetdone	std_logic_vector ( 79 downto 0 )
mgt_SOFT_RESET_TX_IN	std_logic_vector ( 19 downto 0 )
mgt_SOFT_RESET_RX_IN	std_logic_vector ( 19 downto 0 )
tx_resetdone	std_logic_vector ( 79 downto 0 )
mgt_TXUSRCLK_OUT	std_logic_vector ( 79 downto 0 )
mgt_sel_tx_clk	std_logic_vector ( 11 downto 0 )
MGT_RXN_IN	mgt_rx_array ( 19 downto 0 )
MGT_RXP_IN	mgt_rx_array ( 19 downto 0 )
MGT_TXN_IN	mgt_tx_array ( 19 downto 0 )
MGT_TXP_IN	mgt_tx_array ( 19 downto 0 )
rxdata_quad_array	mgt_rxdata_array ( 19 downto 0 )
mgt_txdata	mgt_txdata_array ( 19 downto 0 )
mgt_DATA_VALID_IN	std_logic_vector ( 79 downto 0 )
mgt_loopback_in	mgt_loopback_array ( 19 downto 0 )
mgt_rxchariscomma	mgt_rxchariskcomm_array ( 19 downto 0 )
mgt_rxcharisk	mgt_rxcharisk_array ( 19 downto 0 )
mgt_rxdisperr	mgt_rxdisperr_array ( 79 downto 0 )
mgt_rxnotintable	mgt_rxnotintable_array ( 79 downto 0 )
disperr_error_i	std_logic_vector ( 79 downto 0 )
notable_error_i	std_logic_vector ( 79 downto 0 )
mgt_rx_fsm_resetdone	std_logic_vector ( 79 downto 0 )
mgt_tx_fsm_resetdone	std_logic_vector ( 79 downto 0 )
qpll_fsm_reset_done	std_logic_vector ( 79 downto 0 )
mgt_QPLLLOCK_OUT	std_logic_vector ( 19 downto 0 )
mgt_QPLLREFCLKLOST_OUT	std_logic_vector ( 19 downto 0 )
gt_rxpd	mgt_rxpd_array ( 19 downto 0 )
gt_txpd	mgt_txpd_array ( 19 downto 0 )
mgt_commdet	std_logic_vector ( 0 downto 0 )
tx_bufstatus	std_logic_vector ( 159 downto 0 )
rx_realign	std_logic_vector ( 79 downto 0 )
error_counter_reset	std_logic_vector ( 79 downto 0 )
mgt_loopback_reg	std_logic_vector ( 59 downto 0 )
mgt_txbufstatus	mgt_txbufstatus_array ( 19 downto 0 )
mgt_rxcommadet	mgt_rxcommadet_array ( 19 downto 0 )
mgt_rxbyterealign	mgt_rxbyterealign_array ( 19 downto 0 )
mgt_rx_resetdone	mgt_rxresetdone_array ( 19 downto 0 )
mgt_rxbyteisaligned	mgt_rxbyteisaligned_array ( 19 downto 0 )
mgt_tx_resetdone	mgt_txresetdone_array ( 19 downto 0 )
mgt_txcharisk	mgt_txcharisk_array ( 19 downto 0 )
rx_disperr_reg	std_logic_vector ( 79 downto 0 )
encode_error_reg	std_logic_vector ( 79 downto 0 )
mgt_DATA_VALID_IN_reg	std_logic_vector ( 79 downto 0 )
rxbyteisaligned	std_logic_vector ( 79 downto 0 )
rxdata_out	std_logic_vector ( 79 downto 0 )
rx_disperr	std_logic_vector ( 319 downto 0 )
txcharisk	std_logic_vector ( 319 downto 0 )
encode_error	std_logic_vector ( 319 downto 0 )
mgt_rxcharisk_reg	std_logic_vector ( 319 downto 0 )
data_readout_0	std_logic_vector ( 223 downto 0 )
data_readout_1	std_logic_vector ( 223 downto 0 )
data_readout_2	std_logic_vector ( 223 downto 0 )
data_readout_3	std_logic_vector ( 223 downto 0 )
bcn_cntr	std_logic_vector ( 11 downto 0 )
enable_mgt	std_logic_vector ( 79 downto 0 )
bcn_synch	std_logic_vector ( 79 downto 0 )
crc_error_chan	std_logic_vector ( 79 downto 0 )
sorted_tau_Valid	std_logic
start_pulse_rst	std_logic
BC_Reg_sel	std_logic_vector ( 319 downto 0 )
mux_sel	std_logic_vector ( 319 downto 0 )
reg224_latch	std_logic_vector ( 63 downto 0 )
ttc_pipe	std_logic_vector ( 63 downto 0 )
delay_latch	std_logic_vector ( 63 downto 0 )
delay_num	std_logic_vector ( 319 downto 0 )
reg224_latch_0	std_logic
reg224_latch_1	std_logic
reg224_latch_2	std_logic
reg224_latch_3	std_logic
rx_realign_0	std_logic
rx_realign_1	std_logic
rx_realign_2	std_logic
rx_realign_3	std_logic
delay_latch_0	std_logic
delay_latch_1	std_logic
delay_latch_2	std_logic
delay_latch_3	std_logic
rx_resetdone_quad111	std_logic
delay_num_0	std_logic_vector ( 3 downto 0 )
delay_num_1	std_logic_vector ( 3 downto 0 )
delay_num_2	std_logic_vector ( 3 downto 0 )
delay_num_3	std_logic_vector ( 3 downto 0 )
rx_disperr_0	std_logic_vector ( 3 downto 0 )
rx_disperr_1	std_logic_vector ( 3 downto 0 )
rx_disperr_2	std_logic_vector ( 3 downto 0 )
rx_disperr_3	std_logic_vector ( 3 downto 0 )
encode_error_0	std_logic_vector ( 3 downto 0 )
encode_error_1	std_logic_vector ( 3 downto 0 )
encode_error_2	std_logic_vector ( 3 downto 0 )
encode_error_3	std_logic_vector ( 3 downto 0 )
bc_cntr_0	std_logic_vector ( 139 downto 0 )
bc_cntr_1	std_logic_vector ( 139 downto 0 )
bc_cntr_2	std_logic_vector ( 139 downto 0 )
bc_cntr_3	std_logic_vector ( 139 downto 0 )
bc_mux_cntr_0	std_logic_vector ( 139 downto 0 )
bc_mux_cntr_1	std_logic_vector ( 139 downto 0 )
bc_mux_cntr_2	std_logic_vector ( 139 downto 0 )
bc_mux_cntr_3	std_logic_vector ( 139 downto 0 )
bcn_ref	std_logic_vector ( 4 downto 0 )
pseudo_orbit	std_logic
comma_0	std_logic
comma_1	std_logic
comma_2	std_logic
comma_3	std_logic
data_eq0	std_logic
data_eq1	std_logic
data_eq2	std_logic
data_eq3	std_logic
data_out_0	std_logic_vector ( 31 downto 0 )
data_out_1	std_logic_vector ( 31 downto 0 )
data_out_2	std_logic_vector ( 31 downto 0 )
data_out_3	std_logic_vector ( 31 downto 0 )
phase_mux_i	std_logic_vector ( 31 downto 0 )
test_data	std_logic_vector ( 33 downto 0 )
rx_data_0	mgt_data
rx_data_1	mgt_data
rx_data_2	mgt_data
rx_data_3	mgt_data
rx_data_4	mgt_data
rx_data_5	mgt_data
rx_data_6	mgt_data
rx_data_7	mgt_data
txdatai_0	std_logic_vector ( 33 downto 0 )
txdatai_1	std_logic_vector ( 33 downto 0 )
txdatai_2	std_logic_vector ( 33 downto 0 )
txdatai_3	std_logic_vector ( 33 downto 0 )
txdatai_4	std_logic_vector ( 33 downto 0 )
txdatai_5	std_logic_vector ( 33 downto 0 )
txdatai_6	std_logic_vector ( 33 downto 0 )
txdatai_7	std_logic_vector ( 33 downto 0 )
txdatai_8	std_logic_vector ( 33 downto 0 )
txdatai_9	std_logic_vector ( 33 downto 0 )
txdatai_10	std_logic_vector ( 33 downto 0 )
txdatai_11	std_logic_vector ( 33 downto 0 )
phase_mux	std_logic_vector ( 319 downto 0 )
sorted_eg_TOB_i_gt0	std_logic_vector ( 33 downto 0 )
sorted_eg_TOB_i_gt1	std_logic_vector ( 33 downto 0 )
sorted_eg_TOB_i_gt2	std_logic_vector ( 33 downto 0 )
sorted_eg_TOB_i_gt3	std_logic_vector ( 33 downto 0 )
sorted_eg_TOB_i_gt4	std_logic_vector ( 33 downto 0 )
sorted_eg_TOB_i_gt5	std_logic_vector ( 33 downto 0 )
sorted_eg_TOB_i_gt6	std_logic_vector ( 33 downto 0 )
sorted_eg_TOB_i_gt7	std_logic_vector ( 33 downto 0 )
error_count_0	unsigned ( 31 downto 0 )
error_count_1	unsigned ( 31 downto 0 )
error_count_2	unsigned ( 31 downto 0 )
error_count_3	unsigned ( 31 downto 0 )
error_count_i	unsigned ( 31 downto 0 )
error_count_i_0	unsigned ( 31 downto 0 )
error_count_4	unsigned ( 31 downto 0 )
error_count_5	unsigned ( 31 downto 0 )
error_count_6	unsigned ( 31 downto 0 )
error_count_7	unsigned ( 31 downto 0 )
clear_error	std_logic
comma_detect_ILA	std_logic
error_counter	std_logic_vector ( 1279 downto 0 )
Q210_SOFT_RESET_TX_IN_i	std_logic
Q210_gt0_txresetdone_i	std_logic
Q210_GT0_TX_FSM_RESET_DONE_i	std_logic
Q210_GT0_RX_FSM_RESET_DONE_i	std_logic
Q210_GT1_TX_FSM_RESET_DONE_i	std_logic
Q210_GT1_RX_FSM_RESET_DONE_i	std_logic
Q210_gt1_txresetdone_i	std_logic
Q210_gt0_cplllock_i	std_logic
Q210_gt1_cplllock_i	std_logic
Q210_gt0_txcharisk	std_logic_vector ( 3 downto 0 )
Q210_gt1_txcharisk	std_logic_vector ( 3 downto 0 )
mgt210_tx_bufstatus_i	std_logic_vector ( 3 downto 0 )
gt0_cpllfbclklost_i	std_logic
gt1_cpllfbclklost_i	std_logic
mgt210_tx_resetdone_i	std_logic_vector ( 1 downto 0 )
mgt210_tx_fsm_resetdone_i	std_logic_vector ( 1 downto 0 )
mgt210_txclk_i	std_logic_vector ( 1 downto 0 )
T_TOB_32b_in_i	AlgoTriggerObject
T_TOB_sync_in_i	std_logic
T_TOB_wr_in_i	std_logic
TOB_BCN_sync	std_logic
TOB_BCN_sync_i	std_logic
TOB_BCN_sync_tau_i	std_logic
TOB_BCN_sync_eg_i	std_logic
TOB_BCN_sync_ii	std_logic
data_merge_BCN_A_i	std_logic
data_merge_BCN_B_i	std_logic
data_merge_BCN_C_i	std_logic
data_merge_BCN_A_ii	std_logic
data_merge_BCN_B_ii	std_logic
data_merge_BCN_C_ii	std_logic
data_to_X_i	std_logic_vector ( 32 downto 0 )
data_to_Y_i	std_logic_vector ( 32 downto 0 )
arr_raw_data_in_i	RAW_data_227_type
TOPO_TOB_out_char	std_logic
TOPO_TOB_out	std_logic_vector ( 31 downto 0 )
RAW_Data_out_char	std_logic
RAW_Data_out	std_logic_vector ( 31 downto 0 )
sorted_eg_TOB_1	std_logic_vector ( 32 downto 0 )
sorted_tau_TOB_1	std_logic_vector ( 32 downto 0 )
tob_eg_in	std_logic_vector ( 511 downto 0 )
tob_tau_in	std_logic_vector ( 511 downto 0 )
TOB_TXOUTCLK_i	std_logic
RAW_TXOUTCLK_i	std_logic
ttc_inform	std_logic_vector ( 3 downto 0 )
ECRID_i	std_logic_vector ( 7 downto 0 )
L1ID_i	std_logic_vector ( 23 downto 0 )
L1A_i	std_logic
BCR_i	std_logic
ECR_i	std_logic
TTC_parity_i	std_logic
privilege_read_i	std_logic
ctrl_RAW_ready_i	std_logic
ctrl_TOB_ready_i	std_logic
sorted_TOB_BCN	std_logic_vector ( 11 downto 0 )
sorted_TOB_BCN_i	std_logic_vector ( 11 downto 0 )
sorted_TOB_BCN_ii	std_logic_vector ( 11 downto 0 )
OUT_TOB_BCN_i	std_logic_vector ( 11 downto 0 )
merged_TOB_BCN_i	std_logic_vector ( 11 downto 0 )
OUT_XTOB_BCN_i	std_logic_vector ( 11 downto 0 )
reset_tmp	std_logic
mgt_sel_BC_Reg_sel	std_logic_vector ( 255 downto 0 )
mgt_sel_mux_sel	std_logic_vector ( 255 downto 0 )
mgt_sel_delay_num	std_logic_vector ( 255 downto 0 )
mgt_sel_bc_cntr_0	std_logic_vector ( 111 downto 0 )
mgt_sel_bc_cntr_1	std_logic_vector ( 111 downto 0 )
mgt_sel_bc_cntr_2	std_logic_vector ( 111 downto 0 )
mgt_sel_bc_cntr_3	std_logic_vector ( 111 downto 0 )
mgt_sel_bc_mux_cntr_0	std_logic_vector ( 111 downto 0 )
mgt_sel_bc_mux_cntr_1	std_logic_vector ( 111 downto 0 )
mgt_sel_bc_mux_cntr_2	std_logic_vector ( 111 downto 0 )
mgt_sel_bc_mux_cntr_3	std_logic_vector ( 111 downto 0 )
mgt_sel_RXUSRCLK_OUT	std_logic_vector ( 63 downto 0 )
mgt_sel_enable_mgt	std_logic_vector ( 63 downto 0 )
mgt_sel_bcn_synch	std_logic_vector ( 63 downto 0 )
mgt_sel_crc_error_chan	std_logic_vector ( 63 downto 0 )
mgt_sel_disperr_error	std_logic_vector ( 63 downto 0 )
mgt_sel_notable_error	std_logic_vector ( 63 downto 0 )
mgt_sel_rx_resetdone	std_logic_vector ( 63 downto 0 )
mgt_sel_Commadet	std_logic_vector ( 63 downto 0 )
mgt_sel_Data	mgt_rxdata_array ( 15 downto 0 )
kchar_mgt	std_logic_vector ( 79 downto 0 )
align_frame_mgt	std_logic_vector ( 79 downto 0 )
rxdata_mgt0	std_logic_vector ( 639 downto 0 )
ram_data_mgt0	std_logic_vector ( 4559 downto 0 )
rxdata_mgt1	std_logic_vector ( 639 downto 0 )
ram_data_mgt1	std_logic_vector ( 4559 downto 0 )
rxdata_mgt2	std_logic_vector ( 639 downto 0 )
ram_data_mgt2	std_logic_vector ( 4559 downto 0 )
rxdata_mgt3	std_logic_vector ( 639 downto 0 )
ram_data_mgt3	std_logic_vector ( 4559 downto 0 )
mgt_sel_rxdata_mgt0	std_logic_vector ( 511 downto 0 )
mgt_sel_rxdata_mgt1	std_logic_vector ( 511 downto 0 )
mgt_sel_rxdata_mgt2	std_logic_vector ( 511 downto 0 )
mgt_sel_rxdata_mgt3	std_logic_vector ( 511 downto 0 )
mgt_sel_ram_data_mgt0	std_logic_vector ( 3647 downto 0 )
mgt_sel_ram_data_mgt1	std_logic_vector ( 3647 downto 0 )
mgt_sel_ram_data_mgt2	std_logic_vector ( 3647 downto 0 )
mgt_sel_ram_data_mgt3	std_logic_vector ( 3647 downto 0 )
mgt_sel_kchar	std_logic_vector ( 63 downto 0 )
mgt_sel_align_frame	std_logic_vector ( 63 downto 0 )
fpga_number	integer
sorted_Start_sel	std_logic := ' 0 '
sorted_Start_sel_1	std_logic := ' 0 '
sorted_Start_sel_i	std_logic := ' 0 '
sorted_Start_sel_ii	std_logic := ' 0 '
sorted_Valid_sel	std_logic := ' 0 '
sorted_Valid_sel_1	std_logic := ' 0 '
sorted_Valid_sel_i	std_logic := ' 0 '
sorted_TOB_sel	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
TOB_BCN_sync_reg_i	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
sorted_synch_int	std_logic
sel_bcn_or_bc_cnt_i	std_logic
tob_bc_reg	std_logic_vector ( 31 downto 0 )
tob_bc_status	std_logic_vector ( 31 downto 0 )
TOB_BCN_sync_internal	std_logic
dummy1	std_logic_vector ( 74 downto 0 )
dummy2	std_logic_vector ( 74 downto 0 )
dummy3	std_logic_vector ( 74 downto 0 )
tob_delay_reg	std_logic_vector ( 31 downto 0 )
tob_delay_status	std_logic_vector ( 31 downto 0 )
VAUXP_i	std_logic
VAUXN_i	std_logic
Vp_i	std_logic
Vn_i	std_logic
golden	std_logic
readout_en	std_logic
mgt_en	std_logic
data_path_en	std_logic
input_ram_en	std_logic
output_rams_en	std_logic
merge_en	std_logic
sort_in_ram_en	std_logic
sort_out_ram_en	std_logic
energy_encoding	std_logic_vector ( 1 downto 0 )
dynamic_mapping	std_logic
bcmuxvalue_sych_reg_i	std_logic_vector ( 31 downto 0 )
ttc_orbit_length_reg_i	std_logic_vector ( 31 downto 0 )
probe0	STD_LOGIC_VECTOR ( 34 DOWNTO 0 )
latency_check_in	STD_LOGIC
latency_check_out	STD_LOGIC

Attributes
PRESERVE_SIGNAL	boolean
keep	string
max_fanout	integer
keep	signal is " true "
ASYNC_REG	string
ASYNC_REG	signal is " TRUE "

Instantiations
reset_bufg	bufg
u_1	proc_FPGAs <Entity proc_FPGAs>
global_fabric	ipbus_fabric_sel
common_id	common_id_registers <Entity common_id_registers>
library_reg	lib_registers <Entity lib_registers>
slaves	slaves <Entity slaves>
cclk_o	startup <Entity startup>
configure	self_configure <Entity self_configure>
clock_resources	clk_resources <Entity clk_resources>
f5_to_f1	ibufds
readout_block	Readout_logic_top <Entity Readout_logic_top>
	RAW input data readout signals.
this_to_x	obufds
this_to_y	obufds
data_path_module	data_path_block <Entity data_path_block>
mgt_tx_rx	MGT_4_quad_gen <Entity MGT_4_quad_gen>
mgt_ipb	mgt_slaves <Entity mgt_slaves>
merging_module	IPBusTopMergingModule <Entity IPBusTopMergingModule>
	merge data from fpga2, fpga3 and fpga4
tx_phase_adjust	efex_topo_tx <Entity efex_topo_tx>
	clock 280MHz
io_delay_a1	io_delay
io_delay_a2	io_delay
io_delay_b1	io_delay
io_delay_b2	io_delay
io_delay_c1	io_delay
io_delay_c2	io_delay
io_delay_bc_a	io_delay2
io_delay_bc_b	io_delay2
io_delay_bc_c	io_delay2

Detailed Description

Top of the process FPGA.

This is the top level of the eFEX Processor firmware. The logic implemented here can be grouped into the areas of real-time, readout, control and infrastructure.

Real-Time Logic

This logic implements the core functionality of the eFEX. It forms part of the real-time L1 processing chain that forms the trigger decision. There are 4 Processor FPGAs on the eFEX, and not all of them implement the same real-time logic, as explained below.

Every Processor FPGA performs the following real-time functions:

• Receives 64 channels of serial data at 11.2 Gb/s.
• Transfers these data to the 40.08 MHz LHC clock domain, in the process aligning them to each other and the LHC clock, with a fixed latency.
• Transfers the aligned data to a 200 MHz clock domain and runs electro-magnetic (EM) and Tau feature-extraction algorithms, generating Trigger Objects (TOBs).
• Sorts the EM and Tau TOBs over the FPGA, in order of priority, in the process transfering them to the 280 MHz clock domain. Additionally, 1 Processor FPGAs on every eFEX also performs the following real-time functions.
• Receives EM TOBs from the other 3 Processor FPGAs and sorts them plus its own EM TOBs in order of priority.
• Transmits the 6 highest-priority EM TOBs per BC to Topo, at 11.2 Gb/s. And 1 Processor FPGAs on every eFEX also performs the following real-time functions.
• Receives Tau TOBs from the other 3 Processor FPGAs and sorts them plus its own Tau TOBs in order of priority.
• Transmits the 6 highest-priority Tau TOBs per BC to Topo, at 11.2 Gb/s. Those Processor FPGAs that do not perform this second stage of EM or Tau TOB sorting, transmit their TOBs (either EM or Tau or both) to those FPGAs that do. For each type, up to 6 TOBs are transmitted at 280 Mhz per BC. The real-time logic comprises the following blocks.
• data_path_block (top level of a block that includes data alignment, feature-extraction algorithms and FPGA-level TOB merging)
• IPBusTopMergingModule (module-level TOB merging, plus control interface to that logic. Not implemented in all versions of the Processor FPGA firmware; determined by the generic parameter FLAVOUR.)
• efex_topo_tx (formatting of TOB data for transmission to L1Topo) Readout Logic The readout logic of the Processor FPGA performs the following functions.
• For each BC, the input data, TOBs, and intermediate TOB data (xTOBs) are copied from the real-time logic and held in pipeline memories until the arrival (or not) of the L1A/L0A signal for that BC.
• If an L1A/L0A is received for a BC, some subset of the above data are transmitted downstream on the readout path to the Control FPGA, at 11.2 Gb/s. The subset transmitted depends on the slow-control settings and the current state of the buffer occupancy on the readout path. See the lower levels of the firmware and [ref to data format doc] for details. All of the readout logic is contained with the following block.
• Readout_logic_top (top level of all readout logic)

Control Interface

The control interface is implemented using IP from the IPBus project, which provides access to registers and RAM space within the firmware. For documentation on IPBus, see https://ipbus.web.cern.ch/introduction/ The control interface comprises the following modules.

• proc_FPGAs (IPBus, UDP slave interface to the Control FPGA)
• ipbus_fabric_sel (address-select logic plus data multiplexers)
• common_id_registers (ID registers)
• lib_registers (registers)
• slaves (IPBus-SPI interface to external components)
• startup (Xilinx IP that provides a user interface FPGA configuration and control signals)
• self_configure (FPGA re-configuration control)
• mgt_slaves (control interface of all MGTs)

Infrastructure

The following blocks implement resources that are used by many or all of the other areas of logic.

• clk_resources (clock resources)
• MGT_4_quad_gen (implements all MGTs in the design)

Example of timing diagram

         ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐
 CLK:  ──┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─┘ └─
         ┌───┐ ┌───┐ ┌─┐ ┌─────┐   ┌─┐ ┌─┐
 SIG1: ──┘   └─┘   └─┘ └─┘     └───┘ └─┘ └
         ┌─────┐   ┌─┐   ┌─┐   ┌───┐
 SIG2: ──┘     └───┘ └───┘ └───┘   └────
       ┬─────┬────┬────┬────┬────┬
 Data: │     │ A1 │ A2 │ X  │    │
       ┴─────┴────┴────┴────┴────┴

Author

Mohammed Syiad

Francesco Gonnella

Saeed Taghavi

Definition at line 202 of file top_efex_processor.vhd.

Member Data Documentation

merging_module

merging_module IPBusTopMergingModule

Instantiation

merge data from fpga2, fpga3 and fpga4

sorted and merged Tob data

Definition at line 1575 of file top_efex_processor.vhd.

tx_phase_adjust

tx_phase_adjust efex_topo_tx

Instantiation

clock 280MHz

txdata of quad 211 mgt3

Definition at line 1604 of file top_efex_processor.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/top/top_efex_processor.vhd