top_efex_control Entity Reference

This is the top level of the Control FPGA. More...

Inheritance diagram for top_efex_control:

Entities
spec	architecture
	This is the top level of the Control FPGA. More...

Libraries
ieee
ipbus_lib
unisim
infrastructure_lib

Use Clauses
std_logic_1164
numeric_std
ipbus
VComponents
all
mgt_type	Package <mgt_type>
ProcessorFPGAPackage	Package <ProcessorFPGAPackage>
ipbus_decode_L1CaloEfex	Package <ipbus_decode_L1CaloEfex>
packet_mux_type	Package <packet_mux_type>
golden	Package <golden>

Generics
FLAVOUR	integer := 0
	Integer used to distinguish different FPGAs having a slightly different firmware.
GLOBAL_DATE	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Date format DDMMYYYY in decimal.
GLOBAL_TIME	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Time format 00HHMMSS in decimal.
GLOBAL_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the repository.
GLOBAL_VER	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of the repository (format: MMmmcccc in hex)
XML_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the XMLs.
XML_VER	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of the XMLs.
TOP_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the top folder: list file, xdcs, XMLs, tcl file and this file.
TOP_VER	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of the top folder, see TOP_SHA.
HOG_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the Hog submodule.
HOG_VER	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
CON_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the Hog submodule.
CON_VER	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
INFRASTRUCTURE_LIB_VER	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of infrastructure library (format: MMmmcccc in hex)
INFRASTRUCTURE_LIB_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA.
IPBUS_LIB_SHA	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the ipbus submodule.
IPBUS_LIB_VER	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of the readout library (format: MMmmpppp in hex)
N_PROCESSORFPGA	positive := 4
	number of Processor FPGA instantiated in top_mgt_cfgpa
GOLDEN	boolean := false

Ports
gt_clk125_p	in	std_logic
gt_clk125_n	in	std_logic
gmii_gtx_clk	out	std_logic
gmii_tx_en	out	std_logic
gmii_tx_er	out	std_logic
gmii_txd	out	std_logic_vector ( 7 downto 0 )
gmii_rx_clk	in	std_logic
gmii_rx_dv	in	std_logic
gmii_rx_er	in	std_logic
gmii_rxd	in	std_logic_vector ( 7 downto 0 )
phy_rstb	out	std_logic
clk_40_n	in	std_logic
clk_40_p	in	std_logic
i2c_scl	out	std_logic
i2c_sda	inout	std_logic
i2c_rst_0	out	std_logic
pll_miso	in	std_logic
pll_le_1	out	std_logic
pll_le_3	out	std_logic
pll_clko	out	std_logic
pll_mosi	out	std_logic
pll_lock_1	in	std_logic
pll_lock_3	in	std_logic
flash_csn	out	std_logic
flash_mosi	out	std_logic
flash_miso	in	std_logic
xtal_ttc_clk_sel	out	std_logic
SYNC_B_CDCE	out	std_logic
POWERDN_B_CDCE	out	std_logic
master_tx_data1	in	std_logic_vector ( 9 downto 0 )
master_tx_data2	in	std_logic_vector ( 9 downto 0 )
master_tx_data3	in	std_logic_vector ( 9 downto 0 )
master_tx_data4	in	std_logic_vector ( 9 downto 0 )
master_rx_data1	out	std_logic_vector ( 9 downto 0 )
master_rx_data2	out	std_logic_vector ( 9 downto 0 )
master_rx_data3	out	std_logic_vector ( 9 downto 0 )
master_rx_data4	out	std_logic_vector ( 9 downto 0 )
master_tx_pause1	out	std_logic
master_tx_pause2	out	std_logic
master_tx_pause3	out	std_logic
master_tx_pause4	out	std_logic
hardware_addr	in	std_logic_vector ( 11 downto 0 )
f5_ipbus_access_led	out	std_logic
f5_user_led_1	out	std_logic
f5_ttc_clk_sel	out	std_logic
fifos_full	out	std_logic := ' 0 '
l1a_stretch	out	std_logic := ' 0 '
fpga1_done	in	std_logic
fpga2_done	in	std_logic
fpga3_done	in	std_logic
fpga4_done	in	std_logic
serial_number	in	std_logic_vector ( 5 downto 0 )
reset_clk125	out	std_logic_vector ( 3 downto 0 )
VAUXP	in	std_logic_vector ( 5 downto 0 )
VAUXN	in	std_logic_vector ( 5 downto 0 )
Vp	in	std_logic
Vn	in	std_logic
ctrl_out	out	efex_control_output
ctrl_in	in	efex_control_input

Detailed Description

This is the top level of the Control FPGA.

Overview

The Control FPGA implements logic in three main functional areas:

• the real-time interface to the TTC
• the readout path
• the slow-control interface of the eFEX including support for the IPBus endpoints on the Processor FPGAs

Real-Time Logic

The TTC 40 MHz clock is received on a dedicated backplane channel, with the TTC information encoded on a second channel in the L1Calo backplane format. In terms of the TTC interface, the Control FPGA implements the following:

• It receives the data over one 6.4 Gb/s MGT link from the Hub module with fixed latency (the 6G4 part of top_mgt_cfpga) using the same first level synchronisation scheme as the Processor FPGAs (top_cntrl_synch)
• It decodes this TTC data and transmits the L1A, BCR, BCR, privileged readout, ECRID and L1ID signals synchronously as 40 MHz parallel signals to the processor FPGAs and buffers this information for use by the readout logic.

Readout Path

On the readout path, the Control FPGA performs the following functions:

• It receives TOB and calorimeter data from the four Processor FPGAs via a total of eight streams of 11.2 Gb/s data (the 11G2 part of top_mgt_cfpga)

The bulk of the readout logic is in packet_block:

• It buffers these data for flow control. (The main readout buffers on the eFEX are on the Processor FPGA. Correspondingly, the RAM resources required here are less than half of those on the Processor FPGAs).
• For the TOB readout it combines all of the data for an event into a single packet, for the Input Data the data for each FPGA remains in separate packets, then for each packet it adds header and trailer words that include TTC information and CRCs

Finally it sends the resultant packet to the L1Calo ROD via the Aurora interfaces that combine four 6.4Gb/s MGT lanes into a single channel to each ROD (aurora_hub2)

All of the above is under the control of a state machine which responds to back pressure from the L1Calo RODs, and can assert it to the Processor FPGAs and if need be assert BUSY.

Slow control and IPBus infrastructure

The control interface is implemented using IP from the IPBus project, which provides access to registers and RAM space within the firmware. For documentation on IPBus, see https://ipbus.web.cern.ch/introduction/

The IPBus infrastructure consists of:

• The Ethernet MAC clocks_7s_extphy and eth_7s_gmii (the Control FPGA is the only FPGA on the eFEX that has a physical connection to the Ethernet)
• top_udp_config_FPGA and interconnect (IPBus link layer to Processor FPGAs and local IPBus bus master on Control FPGA)

The local IPBus bus master interfaces to the following modules:

• common_id_registers (ID registers)
• infrastructure_slaves_cntrl (I2C and SPI interfaces)
• aurora_registers (control and status registers for the Aurora interface to the Hub-ROD)
• startup (Xilinx IP that provides a user interface FPGA configuration logic)
• self_configure (FPGA re-configuration control)
• pll_selector (generates PLL enable signals according to input selected)
• nreset_pll (generates reset for PLL)

  Author

  Mohammed Siyad

  David Sankey

Definition at line 70 of file top_efex_control.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/top/top_efex_control.vhd