packet_block Entity Reference

Instantiate the readout merging and routing logic... More...

Inheritance diagram for packet_block:

Entities
rtl	architecture
	Instantiate the readout merging and routing logic... More...

Libraries
ieee
	Use standard library.
ipbus_lib
infrastructure_lib

Use Clauses
std_logic_1164
numeric_std
ipbus
packet_mux_type	Package <packet_mux_type>

Generics
NProcessorFPGA	positive := 4
TOB_FIFO_ADDR_WIDTH	positive := 12
MERGED_FIFO_ADDR_WIDTH	positive := 11
RAW_FIFO_ADDR_WIDTH	positive := 11
TOB_SPY_ADDR_WIDTH	positive := 11
RAW_SPY_ADDR_WIDTH	positive := 11
MERGER_SPY_ADDR_WIDTH	positive := 10
AURORA_SPY_ADDR_WIDTH	positive := 12
MAX_BUILT_PACKET_WIDTH	positive := 8

Ports
clk40	in	std_logic
clk_mgt_bus	in	std_logic_vector ( NProcessorFPGA* 2 - 1 downto 0 )
clk_320	in	std_logic
clk_ipb	in	std_logic
rst_320	in	std_logic
rst_ipb	in	std_logic
eFEX_number	in	std_logic_vector ( 7 downto 0 )
ipb_in	in	ipb_wbus
ipb_out	out	ipb_rbus
bcr_40	in	std_logic
ecr_40	in	std_logic
rst_ttc	in	std_logic
ttc_wr_en	in	std_logic
ttc_rd_en	in	std_logic
ttc_din	in	std_logic_vector ( 49 DOWNTO 0 )
l1a_enable	in	std_logic
source_enable	in	std_logic_vector ( NProcessorFPGA* 2 - 1 downto 0 ) := ( others = > ' 0 ' )
tob_destination_enable	in	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
raw_destination_enable	in	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
data_from_mgt_bus	in	mgt_data_array ( NProcessorFPGA* 2 - 1 downto 0 )
char_is_k_bus	in	std_logic_vector ( NProcessorFPGA* 2 - 1 downto 0 )
error_from_mgt_bus	in	std_logic_vector ( NProcessorFPGA* 2 - 1 downto 0 )
payload_data_bus	out	packet_data_array ( 1 downto 0 )
payload_valid_bus	out	std_logic_vector ( 1 downto 0 )
payload_last_bus	out	std_logic_vector ( 1 downto 0 )
tready_data_bus	in	std_logic_vector ( 1 downto 0 )
packet_mux_source	out	std_logic_vector ( 7 downto 0 )
tob_xoff_bus	in	std_logic_vector ( 1 downto 0 )
raw_xoff_bus	in	std_logic_vector ( 1 downto 0 )
mgt_xoff_bus	out	std_logic_vector ( NProcessorFPGA* 2 - 1 downto 0 )
busy_bus	out	std_logic_vector ( NProcessorFPGA* 2 - 1 downto 0 )

Detailed Description

Instantiate the readout merging and routing logic...

Instantiate the readout merging and routing logic

Input is array of 8 MGT data streams in physical order (U1 to U4, first TOB then Input Data for each FPGA in turn). Output is array of 2 AXI stream outputs, 1 for each Aurora link

Input and output control are governed by source_enable (bit mask in Processor Number order, TOBs then Input Data) and (tob/raw)_destination_enable (the two RODs). Source enable is self explanatory, tob_destination_enable determines whether ping-pong is used or not, raw__destination_enable the mapping for Input Data Network is defined by sampling these immediately after rst_320 is deasserted.

All enable signals are gated with l1a_enable, including the FIFO write enable signals

The TOB data are rearranged into Processor Number order and mapped into an A and B bank of packet_fifo_blocks, with both output streams active odd events go to bank A, even to bank B, with only one active all events go to that bank.

Similarly the raw data are rearranged into Processor Number order and mapped into a single bank of packet_ram_fifos These cascade into an A and B bank of packet_fifos, with both output streams active odd MGT go to bank A, even to bank B, with only one active all MGT go to that bank.

The TTC FIFO data are routed into an A and B FIFO to match the TOB data routing.

There are then two instances of the TOB merger logic processing the banks A and B into two pairs of packet_fifo_blocks, one for merged packets the other the debug stream.

Finally there are two efex_packet_mux, one for each Aurora stream, each with associated efex_packet_builder and fifo_spy

Author

David Sankey

Definition at line 43 of file packet_block.vhd.

---

The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/packet_block.vhd