fifo_spy Entity Reference

Capture FIFO traffic into IPBus DPRAM64... More...

Inheritance diagram for fifo_spy:

Entities
rtl	architecture
	Capture FIFO traffic into IPBus DPRAM64... More...

Libraries
ieee
	Use standard library.
ipbus_lib
	Use IPbus library.

Use Clauses
std_logic_1164
numeric_std
ipbus

Generics
IPBUS_ADDR_WIDTH	positive := 10

Ports
clk_320	in	std_logic
rst_320	in	std_logic
fifo_data	in	std_logic_vector ( 63 DOWNTO 0 )
fifo_valid	in	std_logic
fifo_last	in	std_logic
fifo_tready	in	std_logic
clk_ipb	in	std_logic
rst_ipb	in	std_logic
rst_ipbus_addr	in	std_logic
ipbus_wraparound	in	std_logic
ipb_in	in	ipb_wbus
ipb_out	out	ipb_rbus

Detailed Description

Capture FIFO traffic into IPBus DPRAM64...

Capture FIFO traffic into IPBus DPRAM64 spy RAM Address 0 contains address of last end of packet Control signal rst_ipbus_addr resets write pointer to start of RAM Control signal enables wraparound in RAM if set to '1', otherwise single pass after rst_ipbus_addr Support

Author

David Sankey

Definition at line 21 of file fifo_spy.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/fifo_spy.vhd