fifo_spy.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
LIBRARY ipbus_lib;
USE ipbus_lib.ipbus.all;
 
ENTITY fifo_spy IS
  GENERIC(
    IPBUS_ADDR_WIDTH    : positive := 10
  );
  port (
--- data to FIFO
    clk_320             : in std_logic;
    rst_320             : in std_logic;
    fifo_data           : in std_logic_vector (63 DOWNTO 0);
    fifo_valid          : in std_logic;
    fifo_last           : in std_logic;
    fifo_tready         : in std_logic;
-- interface to IPBus
    clk_ipb             : in std_logic;
    rst_ipb             : in std_logic;
    rst_ipbus_addr      : in std_logic;
    ipbus_wraparound    : in std_logic;
    ipb_in              : in ipb_wbus;
    ipb_out             : out ipb_rbus
  );
END ENTITY fifo_spy;
 
Architecture rtl of fifo_spy is
 
Component ipbus_dpram64 is
    generic(
        ADDR_WIDTH: positive
    );
    port(
        clk: in std_logic;
        rst: in std_logic;
        ipb_in: in ipb_wbus;
        ipb_out: out ipb_rbus;
        rclk: in std_logic;
        we: in std_logic := '0';
        d: in std_logic_vector(63 downto 0) := (others => '0');
        q: out std_logic_vector(63 downto 0);
        addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0)
    );
End Component ipbus_dpram64;
 
   SIGNAL IPBus_RAM_addr, IPBus_RAM_addr_i : std_logic_vector(IPBUS_ADDR_WIDTH-1 downto 0);
   SIGNAL IPBus_RAM_din, IPBus_RAM_din_i, fifo_data_i : std_logic_vector(63 DOWNTO 0);
   SIGNAL IPBus_RAM_we, IPBus_RAM_we_i, fifo_valid_i, fifo_last_i, fifo_tready_i : std_logic;
 
Begin
 
    IPbus_RAM : ipbus_dpram64
      GENERIC MAP (
        ADDR_WIDTH      => IPBUS_ADDR_WIDTH
      )
      PORT MAP (
        clk             => clk_ipb,
        rst             => rst_ipb,
        ipb_in          => ipb_in,
        ipb_out         => ipb_out,
        rclk            => clk_320,
        we              => IPBus_RAM_we,
        d               => IPBus_RAM_din,
        q               => Open,
        addr            => IPBus_RAM_addr
      );
 
ipbus_ram_block: process(clk_320)
    variable ram_addr, next_addr: unsigned(IPBUS_ADDR_WIDTH-1 downto 0) := (Others => '0');
    constant max_addr: unsigned(IPBUS_ADDR_WIDTH-1 downto 0) := (Others => '1');
    constant min_addr: unsigned(IPBUS_ADDR_WIDTH-1 downto 0) := to_unsigned(1, IPBUS_ADDR_WIDTH);
    variable ram_we, endaddr_pending, we_active: std_logic;
    variable ram_data: std_logic_vector(63 downto 0);
    begin
        if rising_edge(clk_320) then
            ram_we := '0';
            ram_addr := next_addr;
            ram_data := (Others => '0');
            if (rst_320 = '1') or (rst_ipbus_addr = '1') then
                next_addr := min_addr;
                endaddr_pending := '0';
                we_active := '1';
            elsif (fifo_valid_i = '1') and (fifo_tready_i = '1') then
                ram_we := we_active;
                ram_data := fifo_data_i;
                endaddr_pending := fifo_last_i;
                if (next_addr = max_addr) then
                    next_addr := min_addr;
-- Disable WE if wrapping around in RAM and ipbus_wraparound not set
                    we_active := ipbus_wraparound;
                else
                    next_addr := next_addr + 1;
                end if;
            elsif (endaddr_pending = '1') then
                ram_we := we_active;
                ram_addr := (Others => '0');
                ram_data(63 downto IPBUS_ADDR_WIDTH+1) := (Others => '0');
                ram_data(IPBUS_ADDR_WIDTH downto 1) := std_logic_vector(next_addr);
                ram_data(0) := '0';
                endaddr_pending := '0';
            end if;
            IPBus_RAM_we_i <= ram_we
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            IPBus_RAM_din_i <= ram_data
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            IPBus_RAM_addr_i <= std_logic_vector(ram_addr)
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process ipbus_ram_block;
 
fifo_reg_block: process(clk_320)
    begin
        if rising_edge(clk_320) then
            fifo_data_i <= fifo_data
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            fifo_valid_i <= fifo_valid
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            fifo_last_i <= fifo_last
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            fifo_tready_i <= fifo_tready
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process fifo_reg_block;
 
ipbus_ram_reg_block: process(clk_320)
    begin
        if rising_edge(clk_320) then
            IPBus_RAM_din <= IPBus_RAM_din_i
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            IPBus_RAM_addr <= IPBus_RAM_addr_i
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            IPBus_RAM_we <= IPBus_RAM_we_i
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process ipbus_ram_reg_block;
 
END Architecture rtl;