data_path Directory Reference

Files
file	cntrl_crc_checker.vhd [code]
	ttc rxdata crc checker
file	ctrl_synch_latch.vhd [code]
	latch enable for the control FPGA
file	efex_packet_builder.vhd [code]
	AXI-stream version of packet engine...
file	efex_packet_merger.vhd [code]
	MUX to concatenate AXI-stream fragments into single packet...
file	efex_packet_mux.vhd [code]
	AXI-stream MUX into packet engine...
file	efex_tob_processor.vhd [code]
	Instantiate the TOB packet for a single Processor FPGA parsing logic ready for merging...
file	fifo_selector.vhd [code]
	Switch FIFO data to correct stream depending on destination_enable...
file	fifo_spy.vhd [code]
	Capture FIFO traffic into IPBus DPRAM64...
file	first_stage_synch.vhd [code]
	First Stage Synchronisation of the control FPGA.
file	mgt_buffer.vhd [code]
	Second version of packet format engine from MGT through to formatted (sub)block...
file	mgt_readout_receiver.vhd [code]
	Second version of packet format engine...
file	packet_block.vhd [code]
	Instantiate the readout merging and routing logic...
file	packet_fifo.vhd [code]
	Optimised RAM-based single clock packet FIFO.
file	packet_fifo_block.vhd [code]
	Instantiate a Block RAM storage and Distributed RAM AXI interface block...
file	packet_fifo_reset_block.vhd [code]
	Assert reset on error in FIFO and hold until end of incoming packet...
file	packet_ram_fifo.vhd [code]
	Optimised RAM-based single clock packet FIFO.
file	packet_status_block.vhd [code]
	Instantiate the readout merging and routing FIFO status and control interface to IPBus...
file	packet_tide_mark_block.vhd [code]
	Instantiate tide mark calculation for a set of 16 bit values...
file	rdout_err_cnt.vhd [code]
	Control FPGA readout counter registers.
file	rdout_ipb_slave.vhd [code]
	Control FPGA data_path slave registers.
file	rdout_monitor.vhd [code]
	Control Readout FIFO level Monitor.
file	srl16e_cntrl.vhd [code]
	shift register
file	top_ctrl_synch.vhd [code]
	Top Synchronisation of the control FPGA.
file	ttc_crc_sm.vhd [code]
	ttc crc sm rxdata crc checker
file	ttc_fifo_block.vhd [code]
	Switch TTC FIFO data to correct stream depending on destination_enable...