efex_tob_processor.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
LIBRARY infrastructure_lib;
use infrastructure_lib.packet_mux_type.all;
 
entity efex_tob_processer is
  GENERIC(
    DEBUG_FORMAT_VERSION    : std_logic_vector (2 DOWNTO 0) := "001"
  );
  port (
    clk                 : in std_logic;
    rst_clk             : in std_logic;
-- TTC input signals
    ttc_info            : IN std_logic_vector(49 DOWNTO 0);
    ttc_valid           : IN std_logic;
-- Input pFPGA TOB packet
    input_fifo_empty    : IN std_logic;
    input_tob_data      : IN std_logic_vector(63 downto 0);
    input_tob_valid     : IN std_logic;
    input_tob_last      : IN std_logic;
    input_tob_ready     : OUT std_logic;
-- Output FIFO signals (0 - TOB merging, 1 - debug)
    output_fifo_data    : OUT packet_data_array(1 downto 0);
    output_fifo_valid   : OUT std_logic_vector(1 downto 0);
    output_fifo_last    : OUT std_logic_vector(1 downto 0);
    output_fifo_ready   : IN std_logic_vector(1 downto 0);
-- Status signals
    TOB_packet_ready    : OUT std_logic;
    TOB_packet_to_merge : OUT std_logic;
    TOB_packet_missing  : OUT std_logic;
    debug_packet_created    : OUT std_logic
  );
end entity efex_tob_processer;
 
Architecture rtl of efex_tob_processer is
 
component efex_packet_merger is
  generic(NSRC: positive := 4);
  port (
    clk                 : in std_logic;
    rst_clk             : in std_logic;
    packet_merger_start : in std_logic := '0';
    packet_merger_enabled  : IN std_logic_vector(NSRC-1 downto 0);
    packet_merger_source   : OUT std_logic_vector(2 downto 0);
    packet_merger_data  : IN packet_data_array(NSRC-1 downto 0);
    packet_merger_valid : IN std_logic_vector(NSRC-1 downto 0);
    packet_merger_last  : IN std_logic_vector(NSRC-1 downto 0);
    packet_merger_ready : OUT std_logic_vector(NSRC-1 downto 0);
    packet_data         : OUT std_logic_vector (63 DOWNTO 0) ;
    packet_valid        : OUT std_logic;
    packet_last         : OUT std_logic;
    packet_sub_last     : OUT std_logic;
    packet_ready        : IN std_logic
  );
end component efex_packet_merger;
 
COMPONENT SRLC32E is
    generic(
        INIT     : std_logic_vector(31 downto 0) := (Others => '0')
    );
    port(
        CLK : in std_logic;
        D : in std_logic;
        CE : in std_logic;
        A : in std_logic_vector(4 downto 0);
        Q : out std_logic;
        Q31 : out std_logic
    );
end COMPONENT SRLC32E;
 
TYPE STATE_TYPE IS (
    idle,
    prepare_l1id,
    parse_l1id,
    check_l1id,
    start_debug_merger,
    send_debug_header,
    send_debug,
    wait_fifo,
    send_status,
    skip_payload_header,
    send_payload,
    end_event
);
 
signal header_sig: std_logic_vector(63 downto 0);
signal start_debug_merger_sig, header_valid_sig, header_ready_sig, debug_ready_sig, l1id_correct_sig, event_missing_sig, fifo_delay_start, fifo_delay_end: std_logic;
signal state_sig: STATE_TYPE;
 
Begin
 
-- map input onto TOB output when state_sig = send_payload
output_fifo_data(0) <= input_tob_data;
output_fifo_valid(0) <= input_tob_valid when (state_sig = send_payload) else '0';
output_fifo_last(0) <= input_tob_last;
 
ready_mux: with state_sig select
    input_tob_ready <= debug_ready_sig when send_debug,
        '1' when skip_payload_header,
        output_fifo_ready(0) when send_payload,
        '0' when Others;
 
-- debug packet with extra header
Debug_packet_merger : efex_packet_merger
    GENERIC MAP (
        NSRC => 2
    )
    PORT MAP (
        clk                 => clk,
        rst_clk             => rst_clk,
        packet_merger_start => start_debug_merger_sig,
        packet_merger_enabled => "11",
        packet_merger_source => OPEN,
        packet_merger_data(0) => header_sig,
        packet_merger_data(1) => input_tob_data,
        packet_merger_valid(0) => header_valid_sig,
        packet_merger_valid(1) => input_tob_valid,
        packet_merger_last(0) => header_valid_sig,
        packet_merger_last(1) => input_tob_last,
        packet_merger_ready(0) => header_ready_sig,
        packet_merger_ready(1) => debug_ready_sig,
        packet_data         => output_fifo_data(1),
        packet_valid        => output_fifo_valid(1),
        packet_last         => output_fifo_last(1),
        packet_sub_last     => OPEN,
        packet_ready        => output_fifo_ready(1)
    );
 
send_debug_block:  process(clk)
variable header_valid: std_logic;
begin
    if rising_edge(clk) then
        if (state_sig = send_debug_header) then
            header_valid := '1';
        else
            header_valid := '0';
        end if;
        header_valid_sig <= header_valid
        -- pragma translate_off
        after 2 ns
        -- pragma translate_on
        ;
    end if;
end process send_debug_block;
 
header_block:  process(clk)
variable header: std_logic_vector(63 downto 0) := (Others => '1');
begin
    if rising_edge(clk) then
        if (state_sig = idle) then
            if (ttc_valid = '1') then
                header := ttc_info(43 downto 12) & DEBUG_FORMAT_VERSION & "0" & x"00" & ttc_info(11 downto 0) & x"C0"; -- Phase-I
            else
                header := (Others => '1');
            end if;
        end if;
        header_sig <= header
        -- pragma translate_off
        after 2 ns
        -- pragma translate_on
        ;
    end if;
end process header_block;
 
l1id_correct_block:  process(clk)
variable bcn_match, l1id_match, ecrid_match, l1id_correct: std_logic;
begin
    if rising_edge(clk) then
        case state_sig is
            when idle =>
                l1id_correct := '0';
            when prepare_l1id =>
                if (input_tob_valid = '1') then
                    if (header_sig(19 downto 8) = input_tob_data(19 downto 8)) then
                        bcn_match := '1';
                    else
                        bcn_match := '0';
                    end if;
                    if (header_sig(55 downto 32) = input_tob_data(55 downto 32)) then
                        l1id_match := '1';
                    else
                        l1id_match := '0';
                    end if;
                    if (header_sig(63 downto 56) = input_tob_data(63 downto 56)) then
                        ecrid_match := '1';
                    else
                        ecrid_match := '0';
                    end if;
                else -- no incoming packet...
                    bcn_match := '0';
                    l1id_match := '0';
                    ecrid_match := '0';
                end if;
            when parse_l1id =>
                if (bcn_match = '1') and (l1id_match = '1') and (ecrid_match = '1') then
                    l1id_correct := '1';
                else
                    l1id_correct := '0';
                end if;
            when Others =>
        end case;
        l1id_correct_sig <= l1id_correct
        -- pragma translate_off
        after 2 ns
        -- pragma translate_on
        ;
    end if;
end process l1id_correct_block;
 
event_missing_block:  process(clk)
variable l1id_future, ecrid_future, ecrid_wraparound, event_missing: std_logic;
variable first_strike: std_logic := '1';
variable processed_packet: std_logic := '0';
begin
    if rising_edge(clk) then
        if rst_clk = '1' then
            event_missing := '0';
            processed_packet := '0';
            first_strike := '1';
        Else
            case state_sig is
                when idle =>
                    event_missing := '0';
                when prepare_l1id =>
                    if (input_tob_valid = '1') then
                        if (unsigned(header_sig(55 downto 32)) < unsigned(input_tob_data(55 downto 32))) then
                            l1id_future := '1';
                        else
                            l1id_future := '0';
                        end if;
                        if (unsigned(header_sig(63 downto 56)) < unsigned(input_tob_data(63 downto 56))) then
                            ecrid_future := '1';
                        else
                            ecrid_future := '0';
                        end if;
                        if (header_sig(63 downto 60) = "1111") and (input_tob_data(63 downto 60) = "0000") then
                            ecrid_wraparound := '1';
                        else
                            ecrid_wraparound := '0';
                        end if;
                    else -- no incoming packet, signify it's really not there...
                        l1id_future := '1';
                        ecrid_future := '1';
                        ecrid_wraparound := '1';
                        first_strike := '1';
                        processed_packet := '1'; -- set up first strike for next packet when it arrives...
                    end if;
                when parse_l1id =>
                    if ((l1id_future = '1') or (ecrid_future = '1') or (ecrid_wraparound = '1')) and (first_strike = '1') then
                        event_missing := '1'; -- keep it if first strike on this Processor packet/signify it's really not there
                    else
                        event_missing := '0';
                    end if;
                when start_debug_merger | skip_payload_header => -- moving the current packet on...
                    first_strike := '1';
                    processed_packet := '1';
                when end_event =>
                    if (processed_packet = '1') then
                        first_strike := '1';
                    else
                        first_strike := '0';
                    end if;
                    processed_packet := '0';
                when Others =>
            end case;
        end if;
        event_missing_sig <= event_missing
        -- pragma translate_off
        after 2 ns
        -- pragma translate_on
        ;
    end if;
end process event_missing_block;
 
merger_start_block: process(clk)
begin
    if rising_edge(clk) then
        if (state_sig = start_debug_merger) then
            start_debug_merger_sig <= '1'
            -- pragma translate_off
            after 2 ns
            -- pragma translate_on
            ;
        else
            start_debug_merger_sig <= '0'
            -- pragma translate_off
            after 2 ns
            -- pragma translate_on
            ;
        end if;
    end if;
end process merger_start_block;
 
report_status_block: process(clk)
begin
    if rising_edge(clk) then
        if (state_sig = send_status) then
            TOB_packet_ready <= '1'
            -- pragma translate_off
            after 2 ns
            -- pragma translate_on
            ;
            TOB_packet_to_merge <= l1id_correct_sig
            -- pragma translate_off
            after 2 ns
            -- pragma translate_on
            ;
            TOB_packet_missing <= event_missing_sig
            -- pragma translate_off
            after 2 ns
            -- pragma translate_on
            ;
        else
            TOB_packet_ready <= '0'
            -- pragma translate_off
            after 2 ns
            -- pragma translate_on
            ;
            TOB_packet_to_merge <= '0'
            -- pragma translate_off
            after 2 ns
            -- pragma translate_on
            ;
            TOB_packet_missing <= '0'
            -- pragma translate_off
            after 2 ns
            -- pragma translate_on
            ;
        end if;
        if (state_sig = start_debug_merger) then
            debug_packet_created <= '1'
            -- pragma translate_off
            after 2 ns
            -- pragma translate_on
            ;
        else
            debug_packet_created <= '0'
            -- pragma translate_off
            after 2 ns
            -- pragma translate_on
            ;
        end if;
    end if;
end process report_status_block;
 
SRLC32E_fifo_delay : SRLC32E
    generic map (INIT => X"00000000")
    port map (
    Q   => Open,
    Q31 => fifo_delay_end,          -- SRL cascaded data output
    A   => (Others => '1'),         -- Delay input
    CE  => '1',                     -- Clock enable input
    CLK => clk,                     -- Clock input
    D   => fifo_delay_start         -- SRL data input
    );
 
state_machine:  process(clk)
variable next_state: STATE_TYPE := idle;
variable fifo_start: std_logic;
begin
    if rising_edge(clk) then
        fifo_start := '0';
        if rst_clk = '1' then
            next_state := idle;
        else
            case state_sig is
                when prepare_l1id =>
                    next_state := parse_l1id;
                when parse_l1id =>
                    next_state := check_l1id;
                when check_l1id =>
                    if (l1id_correct_sig = '1') or (event_missing_sig = '1') then
                        next_state := send_status;
                    else
                        next_state := start_debug_merger;
                    end if;
                when start_debug_merger =>
                    next_state := send_debug_header;
                when send_debug_header =>
                    if (header_ready_sig = '1') then
                        next_state := send_debug;
                    else
                        next_state := send_debug_header;
                    end if;
                when send_debug =>
                    if (input_tob_last = '1') and (input_tob_valid = '1') and (debug_ready_sig = '1') then
                        next_state := wait_fifo;
                        fifo_start := '1';
                    else
                        next_state := send_debug;
                    end if;
                when wait_fifo =>
                    if (input_fifo_empty = '1') and (fifo_delay_end = '1') then
                        next_state := send_status;
                    elsif (input_tob_valid = '1') then
                        next_state := prepare_l1id;
                    else
                        next_state := wait_fifo;
                    end if;
                when send_status =>
                    if (l1id_correct_sig = '1') then
                        next_state := skip_payload_header;
                    else
                        next_state := end_event;
                    end if;
                when skip_payload_header =>
                    next_state := send_payload;
                when send_payload =>
                    if (input_tob_last = '1') and (input_tob_valid = '1') and (output_fifo_ready(0) = '1') then
                        next_state := end_event;
                    else
                        next_state := send_payload;
                    end if;
                when end_event =>
                    next_state := idle;
                when others =>  -- idle
                    if (ttc_valid = '1') then
                        next_state := prepare_l1id;
                    else
                        next_state := idle;
                    end if;
            end case;
        end if;
        state_sig <= next_state
        -- pragma translate_off
        after 2 ns
        -- pragma translate_on
        ;
        fifo_delay_start <= fifo_start
        -- pragma translate_off
        after 2 ns
        -- pragma translate_on
        ;
    end if;
end process state_machine;
 
END Architecture rtl;