efex_packet_merger Entity Reference

MUX to concatenate AXI-stream fragments into single packet... More...

Inheritance diagram for efex_packet_merger:

Entities
rtl	architecture
	MUX to concatenate AXI-stream fragments into single packet... More...

Libraries
ieee
infrastructure_lib

Use Clauses
std_logic_1164
numeric_std
packet_mux_type	Package <packet_mux_type>

Generics
NSRC	positive := 4

Ports
clk	in	std_logic
rst_clk	in	std_logic
packet_merger_start	in	std_logic := ' 0 '
packet_merger_enabled	in	std_logic_vector ( NSRC- 1 downto 0 )
packet_merger_source	out	std_logic_vector ( 2 downto 0 )
packet_merger_data	in	packet_data_array ( NSRC- 1 downto 0 )
		Input signals.
packet_merger_valid	in	std_logic_vector ( NSRC- 1 downto 0 )
packet_merger_last	in	std_logic_vector ( NSRC- 1 downto 0 )
packet_merger_ready	out	std_logic_vector ( NSRC- 1 downto 0 )
packet_data	out	std_logic_vector ( 63 DOWNTO 0 )
		FIFO signals.
packet_valid	out	std_logic
packet_last	out	std_logic
packet_sub_last	out	std_logic
packet_ready	in	std_logic

Detailed Description

MUX to concatenate AXI-stream fragments into single packet...

MUX to concatenate AXI-stream fragments into single packet...

Single pass initiated by asserting packet_merger_start over enabled inputs concatenating fragments into a single packet. last on each input is used to flag immediate switch to next stream and is suppressed to output.

Intermediate inputs can be disabled, but last defined input needs to enabled and last on this input is used as the real output AXI last

Heavily based on IPBus mac_arbiter: "Arbitrates access by several packet sources to a single MAC core This version implements simple round-robin polling.

Dave Newbold, March 2011"

Author

David Sankey

Definition at line 27 of file efex_packet_merger.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/efex_packet_merger.vhd