rtl Architecture Reference

MUX to concatenate AXI-stream fragments into single packet... More...

Processes
select_block	( clk )

Types
STATE_TYPE	( idle , searching , pause , active )
packet_source_array	array ( natural range <> ) of unsigned ( 2 downto 0 )

Signals
src	unsigned ( 2 downto 0 ) := ( others = > ' 0 ' )
next_src	unsigned ( 2 downto 0 ) := ( others = > ' 0 ' )
sel	integer range 0 to NSRC- 1 := 0
next_sel	integer range 0 to NSRC- 1 := 0
source_array	packet_source_array ( NSRC- 1 downto 0 )
state	STATE_TYPE

Detailed Description

MUX to concatenate AXI-stream fragments into single packet...

MUX to concatenate AXI-stream fragments into single packet...

Single pass initiated by asserting packet_merger_start over enabled inputs concatenating fragments into a single packet. last on each input is used to flag immediate switch to next stream and is suppressed to output.

Intermediate inputs can be disabled, but last defined input needs to enabled and last on this input is used as the real output AXI last

Heavily based on IPBus mac_arbiter: "Arbitrates access by several packet sources to a single MAC core This version implements simple round-robin polling.

Dave Newbold, March 2011"

Author

David Sankey

Definition at line 50 of file efex_packet_merger.vhd.

---

The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/efex_packet_merger.vhd