efex_packet_merger.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
LIBRARY infrastructure_lib;
use infrastructure_lib.packet_mux_type.all;
 
entity efex_packet_merger is
  generic(NSRC: positive := 4);
  port (
    clk                 : in std_logic;
    rst_clk             : in std_logic;
    packet_merger_start : in std_logic := '0';
    packet_merger_enabled  : IN std_logic_vector(NSRC-1 downto 0);
    packet_merger_source   : OUT std_logic_vector(2 downto 0);
    packet_merger_data  : IN packet_data_array(NSRC-1 downto 0);
    packet_merger_valid : IN std_logic_vector(NSRC-1 downto 0);
    packet_merger_last  : IN std_logic_vector(NSRC-1 downto 0);
    packet_merger_ready : OUT std_logic_vector(NSRC-1 downto 0);
    packet_data         : OUT std_logic_vector (63 DOWNTO 0) ;
    packet_valid        : OUT std_logic;
    packet_last         : OUT std_logic;
    packet_sub_last     : OUT std_logic;
    packet_ready        : IN std_logic
  );
end efex_packet_merger;
 
architecture rtl of efex_packet_merger is
 
    TYPE STATE_TYPE IS (
        idle,
        searching,
        pause,
        active
    );
    type packet_source_array is array(natural range <>) of unsigned(2 downto 0);
 
    signal src, next_src: unsigned(2 downto 0) := (Others => '0'); -- Up to 8 sources...
    signal sel, next_sel: integer range 0 to NSRC - 1 := 0;
    signal source_array: packet_source_array(NSRC-1 downto 0);
    signal state: STATE_TYPE;
 
begin
 
    sel <= to_integer(src);
    next_sel <= to_integer(next_src);
    packet_merger_source <= std_logic_vector(src);
 
select_block: process(clk)
    begin
        if rising_edge(clk) then
            if (rst_clk = '1') then
                state <= idle;
                src <= "000";
                next_src <= to_unsigned(NSRC-1, 3);
                source_array <= (Others => (Others => '0'));
            else
                case state is
                when searching =>
-- first load LIFO with enabled sources in reverse order
                    if (packet_merger_enabled(next_sel) = '1') then
                        source_array <= source_array(NSRC-2 downto 0) & next_src;
                    end if;
                    if next_src /= "000" then
                        next_src <= next_src - 1;
                    else
                        state <= pause;
                    end if;
                when pause =>
-- start with first enabled source
                    src <= source_array(0);
                    source_array <= "000" & source_array(NSRC-1 downto 1);
                    state <= active;
                when active =>
-- then switch to next source on each input last signal
                    if (packet_merger_last(sel) = '1') and (packet_ready = '1') then  -- End of data on this input...
                        if (sel = NSRC-1) then -- and it was the last input
                            src <= "000";
                            state <= idle;
                        else
                            src <= source_array(0);
                            source_array <= "000" & source_array(NSRC-1 downto 1);
                        end if;
                    end if;
                when Others =>
                    if (packet_merger_start = '1') then
                        src <= "000";
                        next_src <= to_unsigned(NSRC-1, 3);
                        state <= searching;
                    end if;
                end case;
            end if;
        end if;
    end process select_block;
 
-- mask signal when hunting for data...
    packet_valid <= packet_merger_valid(sel) when (state = active) else '0';
    packet_data <= packet_merger_data(sel);
-- report suppressed last embedded within the packet
    packet_sub_last <= packet_merger_last(sel);
-- only enable output last when on last input...
    packet_last <= packet_merger_last(NSRC-1) when (sel = NSRC-1) else '0';
 
    ackgen: for i in NSRC - 1 downto 0 generate
    begin
        packet_merger_ready(i) <= packet_ready when (sel = i) and (state = active) else '0';
    end generate;
 
end rtl;