efex_tob_processor.vhd File Reference

Instantiate the TOB packet for a single Processor FPGA parsing logic ready for merging... More...

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Entities
efex_tob_processer	entity
rtl	architecture

Detailed Description

Instantiate the TOB packet for a single Processor FPGA parsing logic ready for merging...

Instantiate the TOB packet parsing logic for a single Processor FPGA parsing logic

Input is the preformatted TOB packet AXI stream from a Processor FPGA, along with expected L1ID and BCN for merging.

Output is array of 2 AXI stream outputs, 1 validated TOB packet into the actual merger less the common header, the other complete Debug packet for any invalid TOB packets, along with status for merger block.

Author

David Sankey

Definition in file efex_tob_processor.vhd.