rtl Architecture Reference

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Processes
send_debug_block	( clk )
header_block	( clk )
l1id_correct_block	( clk )
event_missing_block	( clk )
merger_start_block	( clk )
report_status_block	( clk )
state_machine	( clk )

Components
efex_packet_merger	<Entity efex_packet_merger>
	Input signals.
SRLC32E
	FIFO signals.

Types
STATE_TYPE	( idle , prepare_l1id , parse_l1id , check_l1id , start_debug_merger , send_debug_header , send_debug , wait_fifo , send_status , skip_payload_header , send_payload , end_event )

Signals
header_sig	std_logic_vector ( 63 downto 0 )
start_debug_merger_sig	std_logic
header_valid_sig	std_logic
header_ready_sig	std_logic
debug_ready_sig	std_logic
l1id_correct_sig	std_logic
event_missing_sig	std_logic
fifo_delay_start	std_logic
fifo_delay_end	std_logic
state_sig	STATE_TYPE

Instantiations
debug_packet_merger	efex_packet_merger <Entity efex_packet_merger>
srlc32e_fifo_delay	srlc32e

Detailed Description

Definition at line 52 of file efex_tob_processor.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/efex_tob_processor.vhd