efex_tob_processer Entity Reference

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Inheritance diagram for efex_tob_processer:

Entities
rtl	architecture

Libraries
ieee
	Use standard library.
infrastructure_lib

Use Clauses
std_logic_1164
numeric_std
packet_mux_type	Package <packet_mux_type>

Generics
DEBUG_FORMAT_VERSION	std_logic_vector ( 2 DOWNTO 0 ) := " 001 "

Ports
clk	in	std_logic
rst_clk	in	std_logic
ttc_info	in	std_logic_vector ( 49 DOWNTO 0 )
ttc_valid	in	std_logic
input_fifo_empty	in	std_logic
input_tob_data	in	std_logic_vector ( 63 downto 0 )
input_tob_valid	in	std_logic
input_tob_last	in	std_logic
input_tob_ready	out	std_logic
output_fifo_data	out	packet_data_array ( 1 downto 0 )
output_fifo_valid	out	std_logic_vector ( 1 downto 0 )
output_fifo_last	out	std_logic_vector ( 1 downto 0 )
output_fifo_ready	in	std_logic_vector ( 1 downto 0 )
TOB_packet_ready	out	std_logic
TOB_packet_to_merge	out	std_logic
TOB_packet_missing	out	std_logic
debug_packet_created	out	std_logic

Detailed Description

Definition at line 22 of file efex_tob_processor.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/efex_tob_processor.vhd