eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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packet_block.vhd
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1 
31 
33 LIBRARY ieee;
34 USE ieee.std_logic_1164.all;
35 use ieee.numeric_std.all;
36 
37 LIBRARY ipbus_lib;
38 USE ipbus_lib.ipbus.all;
39 LIBRARY infrastructure_lib;
40 use infrastructure_lib.packet_mux_type.all;
41 
43 ENTITY packet_block IS
44  GENERIC(
45  NProcessorFPGA: positive := 4; -- first TOB then Input Data for each FPGA in turn
46  TOB_FIFO_ADDR_WIDTH: positive := 12; -- size of TOB FIFO RAM in packet_fifo_block for each Processor FPGA
47  MERGED_FIFO_ADDR_WIDTH: positive := 11; -- size of merged FIFO RAMs after TOB merging
48  RAW_FIFO_ADDR_WIDTH: positive := 11; -- size of RAW FIFO RAM in packet_fifo_block for each Processor FPGA
49  TOB_SPY_ADDR_WIDTH: positive := 11; -- size of each Processor FPGA TOB SPY RAM inside mgt_buffer
50  RAW_SPY_ADDR_WIDTH: positive := 11; -- size of each Processor FPGA RAW SPY RAM inside mgt_buffer
51  MERGER_SPY_ADDR_WIDTH: positive := 10; -- NB DPRAM64 so IPBus address width is 1 more
52  AURORA_SPY_ADDR_WIDTH: positive := 12; -- NB DPRAM64 so IPBus address width is 1 more
53  MAX_BUILT_PACKET_WIDTH: positive := 8 -- NB merged FIFOs use this + 2 to account for the 4 FPGAs merged together
54  );
55  PORT (
56 -- clocks etc
57  clk40 : in std_logic;
58  clk_mgt_bus : in std_logic_vector(NProcessorFPGA*2 - 1 downto 0);
59  clk_320 : in std_logic;
60  clk_ipb : in std_logic;
61  rst_320 : in std_logic;
62  rst_ipb : in std_logic;
63 -- eFEX number
64  eFEX_number : in std_logic_vector(7 downto 0);
65 -- IPBus
66  ipb_in : in ipb_wbus;
67  ipb_out : out ipb_rbus;
68 -- TTC data
69  bcr_40 : in std_logic;
70  ecr_40 : in std_logic;
71  rst_ttc : in std_logic;
72  ttc_wr_en : in std_logic;
73  ttc_rd_en : in std_logic;
74  ttc_din : in std_logic_vector(49 DOWNTO 0);
75 -- input and output control
76  l1a_enable : in std_logic; -- used to gate all internal enable signals...
77  source_enable : in std_logic_vector(NProcessorFPGA*2 - 1 downto 0) := (Others => '0'); -- Processor Number order, TOBs then Input Data
78  tob_destination_enable : in std_logic_vector(1 downto 0) := (Others => '0'); -- Output selection for TOBs
79  raw_destination_enable : in std_logic_vector(1 downto 0) := (Others => '0'); -- Output selection for Raw
80 -- data from MGT
81  data_from_mgt_bus : in mgt_data_array(NProcessorFPGA*2 - 1 downto 0); -- first TOB then Input Data for each FPGA in turn in U number order
82  char_is_k_bus : in std_logic_vector(NProcessorFPGA*2 - 1 downto 0); -- first TOB then Input Data for each FPGA in turn in U number order
83  error_from_mgt_bus : in std_logic_vector(NProcessorFPGA*2 - 1 downto 0); -- first TOB then Input Data for each FPGA in turn in U number order
84 -- data to Aurora
85  payload_data_bus : out packet_data_array(1 downto 0);
86  payload_valid_bus : out std_logic_vector(1 downto 0);
87  payload_last_bus : out std_logic_vector(1 downto 0);
88  tready_data_bus : in std_logic_vector(1 downto 0);
89  packet_mux_source : OUT std_logic_vector(7 downto 0); -- Active source (3 downto 0) for each output
90 -- flow control
91  tob_xoff_bus : in std_logic_vector(1 downto 0);
92  raw_xoff_bus : in std_logic_vector(1 downto 0);
93  mgt_xoff_bus : out std_logic_vector(NProcessorFPGA*2 - 1 downto 0); -- in Processor Number order, (3 downto 0) TOBs (7 downto 4) Input Data
94  busy_bus : out std_logic_vector(NProcessorFPGA*2 - 1 downto 0) -- in Processor Number order, (3 downto 0) TOBs (7 downto 4) Input Data
95  );
96 END ENTITY packet_block;
97 
99 Architecture rtl of packet_block is
100 
101 Component efex_packet_builder is
102  port (
103  clk : in std_logic;
104  rst_clk : in std_logic;
106  packet_data : IN std_logic_vector (63 DOWNTO 0) ;
107  packet_valid : IN std_logic;
108  packet_last : IN std_logic;
109  packet_ready : OUT std_logic;
111  payload_data : OUT std_logic_vector (63 DOWNTO 0) ;
112  payload_valid : OUT std_logic;
113  payload_last : OUT std_logic;
114  tready_data : IN std_logic
115  );
116 end Component efex_packet_builder;
117 
118 Component efex_packet_mux is
119  generic(NSRC: positive := 4);
120  port (
121  clk : in std_logic;
122  rst_clk : in std_logic;
123 -- Shelf and eFEX number (for error recovery trailer)
124  eFEX_number : in std_logic_vector(7 downto 0);
125  pause : in std_logic := '0';
126  packet_mux_enabled : IN std_logic_vector(NSRC-1 downto 0);
127  packet_mux_reset : IN std_logic_vector(NSRC-1 downto 0);
128  packet_mux_source : OUT std_logic_vector(3 downto 0);
130  packet_mux_data : IN packet_data_array(NSRC-1 downto 0);
131  packet_mux_valid : IN std_logic_vector(NSRC-1 downto 0);
132  packet_mux_last : IN std_logic_vector(NSRC-1 downto 0);
133  packet_mux_ready : OUT std_logic_vector(NSRC-1 downto 0);
135  packet_data : OUT std_logic_vector (63 DOWNTO 0) ;
136  packet_valid : OUT std_logic;
137  packet_last : OUT std_logic;
138  packet_ready : IN std_logic
139  );
140 end Component efex_packet_mux;
141 
142 Component fwft_register is
143  GENERIC(
144  DATA_WIDTH: positive := 64
145  );
146  Port (
147  clk : in std_logic;
148  rst_clk : in std_logic;
149 -- Input signals
150  in_data : IN std_logic_vector(DATA_WIDTH-1 DOWNTO 0);
151  in_valid : IN std_logic;
152  in_ready : OUT std_logic;
153 -- Output signals
154  out_data : OUT std_logic_vector(DATA_WIDTH-1 DOWNTO 0);
155  out_valid : OUT std_logic;
156  out_ready : IN std_logic
157  );
158 end Component fwft_register;
159 
160 Component mgt_buffer IS
161  GENERIC(
162  INPUT_FPGA_NO : std_logic_vector(1 downto 0) := "00";
163  DATA_FORMAT_VERSION : std_logic_vector (2 DOWNTO 0) := "001";
164  IPBUS_ADDR_WIDTH : positive := 10;
165  ILA_ENABLED : std_logic := '0'
166  );
167  port (
168 -- Static signals
169  eFEX_number : IN std_logic_vector(7 downto 0); -- Shelf Address and eFEX number
170  enable : in std_logic;
171 -- data from MGT
172  clk_mgt : in std_logic;
173  data_from_mgt : in std_logic_vector(31 downto 0);
174  char_is_k : in std_logic;
175  error_from_mgt : in std_logic;
176 -- data to FIFO
177  clk_320 : in std_logic;
178  rst_320 : in std_logic;
179  fifo_data : out std_logic_vector (63 DOWNTO 0);
180  fifo_valid : out std_logic;
181  fifo_last : out std_logic;
182 -- status signals
183  mgt_last_l1id : out std_logic_vector (31 downto 0);
184  mgt_packet_stats : out std_logic_vector (4 downto 0);
185 -- interface to IPBus
186  clk_ipb : in std_logic;
187  rst_ipb : in std_logic;
188  rst_ipbus_addr : in std_logic;
189  ipbus_wraparound : in std_logic;
190  ipb_in : in ipb_wbus;
191  ipb_out : out ipb_rbus
192  );
193 END Component mgt_buffer;
194 
195 Component efex_tob_merger is
196  GENERIC(
197  DATA_FORMAT_VERSION : std_logic_vector (2 DOWNTO 0) := "001"
198  );
199  port (
200  clk : in std_logic;
201  rst_clk : in std_logic;
202 -- eFEX number
203  eFEX_number : in std_logic_vector(7 downto 0);
204 -- Control signals
205  ifg_duration : IN std_logic_vector(3 downto 0);
206  fpga_tob_enabled : IN std_logic_vector(3 downto 0);
207  pause : IN std_logic_vector(1 downto 0);
208 -- TTC FIFO signals
209  ttc_rd_en : OUT STD_LOGIC;
210  ttc_dout : IN std_logic_vector(49 DOWNTO 0);
211  ttc_fifo_empty : IN STD_LOGIC;
212 -- Input pFPGA TOB packets
213  input_fifo_empty : IN std_logic_vector(3 downto 0);
214  fpga_tob_data : IN packet_data_array(3 downto 0);
215  fpga_tob_valid : IN std_logic_vector(3 downto 0);
216  fpga_tob_last : IN std_logic_vector(3 downto 0);
217  fpga_tob_ready : OUT std_logic_vector(3 downto 0);
218 -- Output FIFO signals
219  merged_fifo_data : OUT packet_data_array(1 downto 0);
220  merged_fifo_valid : OUT std_logic_vector(1 downto 0);
221  merged_fifo_last : OUT std_logic_vector(1 downto 0);
222 -- Status signals
223  L1A_seen : OUT STD_LOGIC;
224  Last_L1ID_merged : OUT std_logic_vector(31 downto 0); -- ECRID and L1ID
225  TOB_packet_merged_bus : OUT std_logic_vector(3 downto 0);
226  TOB_packet_missing_bus : OUT std_logic_vector(3 downto 0);
227  debug_packet_created_bus : OUT std_logic_vector(3 downto 0)
228  );
229 end Component efex_tob_merger;
230 
231 Component fifo_selector IS
232  port (
233  clk_320 : in std_logic;
234 -- FIFO data from MGT block
235  fifo_data : in std_logic_vector (63 DOWNTO 0);
236  fifo_valid : in std_logic;
237  fifo_last : in std_logic;
238 -- data to FIFO A
239  fifo_data_A : out std_logic_vector (63 DOWNTO 0);
240  fifo_valid_A : out std_logic;
241  fifo_last_A : out std_logic;
242 -- data to FIFO B
243  fifo_data_B : out std_logic_vector (63 DOWNTO 0);
244  fifo_valid_B : out std_logic;
245  fifo_last_B : out std_logic;
246 -- switch control
247  destination_enable : in std_logic_vector(1 downto 0) := (Others => '0')
248  );
249 END Component fifo_selector;
250 
251 Component packet_fifo_block IS
252  GENERIC(
253  RAM_ADDR_WIDTH : positive := 12;
254  MAX_PACKET_WIDTH : positive := 8
255  );
256  port (
257  clk_320 : in std_logic;
258  rst_320 : in std_logic;
259 --
260  fifo_data : in std_logic_vector (63 DOWNTO 0);
261  fifo_valid : in std_logic;
262  fifo_last : in std_logic;
263 --
264  packet_data : OUT std_logic_vector (63 DOWNTO 0);
265  packet_valid : OUT std_logic;
266  packet_last : OUT std_logic;
267  packet_ready : IN std_logic;
268 --
269  fifo_fill_level : out std_logic_vector(15 downto 0);
270  packet_count : out STD_LOGIC_VECTOR(15 downto 0);
271  fifo_empty : OUT std_logic;
272  input_error : OUT std_logic;
273  fifo_error : OUT std_logic
274  );
275 END Component packet_fifo_block;
276 
277 Component packet_ram_fifo is
278  Generic (
279  DATA_WIDTH: positive := 64;
280  constant BUFWIDTH: positive := 10;
281  constant MAXWIDTH: positive := 5
282  );
283  Port (
284  clk : in STD_LOGIC;
285  rst_clk : in STD_LOGIC;
286  in_data : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
287  in_valid : in STD_LOGIC;
288  in_last : in STD_LOGIC;
289  out_pause : in STD_LOGIC;
290  out_data : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
291  out_valid : out STD_LOGIC;
292  out_last : out STD_LOGIC;
293  fifo_fill_level : out STD_LOGIC_VECTOR(15 downto 0);
294  packet_count : out STD_LOGIC_VECTOR(15 downto 0);
295  in_error : out STD_LOGIC;
296  out_error : out STD_LOGIC
297  );
298 end Component packet_ram_fifo;
299 
300 Component packet_fifo is
301  Generic (
302  DATA_WIDTH: positive := 64;
303  constant BUFWIDTH: positive := 4
304  );
305  Port (
306  clk : in STD_LOGIC;
307  rst_clk : in STD_LOGIC;
308  in_data : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
309  in_valid : in STD_LOGIC;
310  in_last : in STD_LOGIC;
311  in_pause : out STD_LOGIC;
312  out_ready : in STD_LOGIC;
313  out_data : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
314  out_valid : out STD_LOGIC;
315  out_last : out STD_LOGIC;
316  out_error : out STD_LOGIC
317  );
318 end Component packet_fifo;
319 
320 Component packet_fifo_reset_block IS
321  Port (
322  clk : in std_logic;
323  rst : in std_logic;
324  fifo_valid : in std_logic;
325  fifo_last : in std_logic;
326  fifo_error : in std_logic;
327  fifo_reset : out std_logic
328  );
329 End Component packet_fifo_reset_block;
330 
331 Component ttc_fifo_block IS
332  generic(
333  DELAY_DEPTH : Integer range 0 to 255 := 3 -- Number of SRLC32E to cascade for delayed L1A strobe over and above ftm_ttc_mode delay
334  );
335  PORT (
336 -- clocks etc
337  clk40 : in std_logic;
338  clk_320 : in std_logic;
339 -- TTC input FIFO
340  rst_ttc : in std_logic;
341  ttc_wr_en : in std_logic;
342  ttc_rd_en : in std_logic;
343  ttc_din : in std_logic_vector(49 DOWNTO 0);
344 -- TTC output FIFOs
345  ttc_rd_en_A : in std_logic;
346  ttc_empty_A : out std_logic;
347  ttc_dout_A : out std_logic_vector(49 DOWNTO 0);
348  ttc_rd_en_B : in std_logic;
349  ttc_empty_B : out std_logic;
350  ttc_dout_B : out std_logic_vector(49 DOWNTO 0);
351 -- input and output control
352  destination_enable : in std_logic_vector(1 downto 0) := (Others => '0');
353  readout_delay : in std_logic_vector(7 downto 0)
354  );
355 END Component ttc_fifo_block;
356 
357 Component fifo_spy IS
358  GENERIC(
359  IPBUS_ADDR_WIDTH : positive := 10
360  );
361  port (
362 --- data to FIFO
363  clk_320 : in std_logic;
364  rst_320 : in std_logic;
365  fifo_data : in std_logic_vector (63 DOWNTO 0);
366  fifo_valid : in std_logic;
367  fifo_last : in std_logic;
368  fifo_tready : in std_logic;
369 -- interface to IPBus
370  clk_ipb : in std_logic;
371  rst_ipb : in std_logic;
372  rst_ipbus_addr : in std_logic;
373  ipbus_wraparound : in std_logic;
374  ipb_in : in ipb_wbus;
375  ipb_out : out ipb_rbus
376  );
377 END Component fifo_spy;
378 
379 Component tob_merger_spy is
380  GENERIC(
381  RAM_ADDR_WIDTH : positive := 10
382  );
383  port (
384  clk_320 : in std_logic;
385  rst_320 : in std_logic;
386 -- TOB MGT status signals
387  tob_mgt_packet_err_bus : in std_logic_vector(3 downto 0);
388  tob_mgt_length_err_bus : in std_logic_vector(3 downto 0);
389  tob_mgt_last_l1id_bus : in mgt_data_array(3 downto 0);
390 -- Merger status signals
391  L1A_seen : in std_logic;
392  Last_L1ID_merged : in std_logic_vector(31 downto 0); -- ECRID and L1ID
393 -- Merger output FIFO signals
394  merged_fifo_data : in packet_data_array(1 downto 0);
395  merged_fifo_valid : in std_logic_vector(1 downto 0);
396  merged_fifo_last : in std_logic_vector(1 downto 0);
397 -- interface to IPBus
398  clk_ipb : in std_logic;
399  rst_ipb : in std_logic;
400  rst_ipbus_addr : in std_logic;
401  ipbus_wraparound : in std_logic;
402  ipb_in : in ipb_wbus;
403  ipb_out : out ipb_rbus
404  );
405 end Component tob_merger_spy;
406 
407 Component packet_status_block IS
408  GENERIC(
409  TOB_FIFO_ADDR_MAX_WIDTH: positive := 12; -- address bus width of TOB FIFO RAM in packet_fifo_block for each Processor FPGA
410  MERGED_FIFO_ADDR_MAX_WIDTH: positive := 11; -- address bus width of merged FIFO RAMs after TOB merging
411  RAW_FIFO_ADDR_MAX_WIDTH: positive := 11; -- address bus width of RAW FIFO RAM in packet_fifo_block for each Processor FPGA
412  MAX_PACKET_WIDTH : positive := 8 -- address bus width of maximum input packet (i.e. 8 implies 256 64 bit words), merged packets can be 4 times larger
413  );
414  PORT (
415 -- clocks etc
416  clk_320 : in std_logic;
417  rst_320 : in std_logic;
418  clk_ipb : in std_logic;
419  rst_ipb : in std_logic;
420  bcr_320 : in std_logic;
421  ecr_320 : in std_logic;
422 -- upstream IPBus
423  ipb_in : in ipb_wbus;
424  ipb_out : out ipb_rbus;
425 -- MGT TOB input spy RAMs
426  ipbus_tob_mgt_wbus_array : out ipb_wbus_array(3 downto 0); -- array of wbus
427  ipbus_tob_mgt_rbus_array : in ipb_rbus_array(3 downto 0); -- array of rbus
428 -- MGT raw input spy RAMs
429  ipbus_raw_mgt_wbus_array : out ipb_wbus_array(3 downto 0);
430  ipbus_raw_mgt_rbus_array : in ipb_rbus_array(3 downto 0);
431 -- Merger debug spy RAMs
432  ipbus_merger_spy_wbus_array : out ipb_wbus_array(1 downto 0);
433  ipbus_merger_spy_rbus_array : in ipb_rbus_array(1 downto 0);
434 -- Aurora output spy RAMs
435  ipbus_built_fifo_wbus_array : out ipb_wbus_array(1 downto 0);
436  ipbus_built_fifo_rbus_array : in ipb_rbus_array(1 downto 0);
437 
438 -- MGT TOB input spy RAM control
439  rst_ipbus_tob_mgt_addr_bus : out std_logic_vector(3 downto 0); -- size of spy RAM 16-bit address
440  ipbus_tob_mgt_wraparound_bus : out std_logic_vector(3 downto 0);
441 -- MGT raw input spy RAM control
442  rst_ipbus_raw_mgt_addr_bus : out std_logic_vector(3 downto 0);
443  ipbus_raw_mgt_wraparound_bus : out std_logic_vector(3 downto 0);
444 -- Merger debug spy RAM control
445  rst_ipbus_merger_spy_addr_bus : out std_logic_vector(1 downto 0);
446  ipbus_merger_spy_wraparound_bus : out std_logic_vector(1 downto 0);
447 -- Aurora output spy RAM control
448  rst_ipbus_built_fifo_addr_bus : out std_logic_vector(1 downto 0);
449  ipbus_built_fifo_wraparound_bus : out std_logic_vector(1 downto 0);
450 -- Readout delay control
451  readout_delay : out std_logic_vector(31 downto 0);
452 -- TOB MGT status
453  tob_mgt_packet_received_bus : in std_logic_vector(3 downto 0);
454  tob_mgt_safe_mode_bus : in std_logic_vector(3 downto 0);
455  tob_mgt_packet_err_bus : in std_logic_vector(3 downto 0);
456  tob_mgt_length_err_bus : in std_logic_vector(3 downto 0);
457  tob_mgt_bcn_err_bus : in std_logic_vector(3 downto 0);
458  tob_mgt_last_l1id_bus : in mgt_data_array(3 downto 0);
459 
460 -- Raw MGT status
461  raw_mgt_packet_received_bus : in std_logic_vector(3 downto 0);
462  raw_mgt_safe_mode_bus : in std_logic_vector(3 downto 0);
463  raw_mgt_packet_err_bus : in std_logic_vector(3 downto 0);
464  raw_mgt_length_err_bus : in std_logic_vector(3 downto 0);
465  raw_mgt_last_l1id_bus : in mgt_data_array(3 downto 0);
466 
467 -- TOB FIFO status block A -- TOB FIFOs have same values, XOFF & BUSY
468  tob_fifo_fill_level_A_bus : in fifo_status_array(3 downto 0); -- array of 16-bits
469  tob_packet_count_A_bus : in fifo_status_array(3 downto 0); -- array of 16-bits
470  tob_fifo_error_A_bus : in std_logic_vector(3 downto 0); -- status to be read by IPBus (if rd & wr pointers crash) to be counted.
471 
472 -- TOB FIFO status block B XOFF & BUSY
473  tob_fifo_fill_level_B_bus : in fifo_status_array(3 downto 0);
474  tob_packet_count_B_bus : in fifo_status_array(3 downto 0);
475  tob_fifo_error_B_bus : in std_logic_vector(3 downto 0);
476 
477 -- L1A status
478  Last_L1ID_merger_A : in std_logic_vector(31 downto 0); -- ECRID and L1ID
479  Last_L1ID_merger_B : in std_logic_vector(31 downto 0);
480  L1A_seen_bus : in std_logic_vector(1 downto 0); -- Merger A (0), Merger B (1)
481 
482 -- TOB merging counts per Processor FPGA
483  TOB_packet_merged_A_bus : in std_logic_vector(3 downto 0);
484  TOB_packet_missing_A_bus : in std_logic_vector(3 downto 0);
485  debug_packet_created_A_bus : in std_logic_vector(3 downto 0);
486  TOB_packet_merged_B_bus : in std_logic_vector(3 downto 0);
487  TOB_packet_missing_B_bus : in std_logic_vector(3 downto 0);
488  debug_packet_created_B_bus : in std_logic_vector(3 downto 0);
489 
490 -- MUX status
491  mux_active_bus : in std_logic_vector(1 downto 0);
492  mux_l1id_valid_bus : in std_logic_vector(1 downto 0);
493  mux_source_bus : in std_logic_vector(7 downto 0);
494  mux_l1id_bus : in mgt_data_array(1 downto 0);
495 
496 -- status bits PAUSE
497  merged_fifo_fill_level_A_bus : in fifo_status_array(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1) 16-bits inputs
498  merged_packet_count_A_bus : in fifo_status_array(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1) 16-bits
499  merged_fifo_error_A_bus : in std_logic_vector(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1) count errors
500 
501 -- status bits PAUSE
502  merged_fifo_fill_level_B_bus : in fifo_status_array(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1)
503  merged_packet_count_B_bus : in fifo_status_array(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1)
504  merged_fifo_error_B_bus : in std_logic_vector(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1)
505 
506 -- Raw FIFO status block XOFF & BUSY
507  raw_fifo_fill_level_bus : in fifo_status_array(3 downto 0); -- 16-bits
508  raw_packet_count_bus : in fifo_status_array(3 downto 0);
509  raw_fifo_error_bus : in std_logic_vector(3 downto 0);
510 
511 -- MGT flow control
512  tob_mgt_xoff_bus : out std_logic_vector(3 downto 0); -- to process FPGA
513  raw_mgt_xoff_bus : out std_logic_vector(3 downto 0);
514 -- BUSY control
515  tob_busy_bus : out std_logic_vector(3 downto 0);
516  raw_busy_bus : out std_logic_vector(3 downto 0);
517 -- Merging block flow control
518  Block_A_pause : out std_logic_vector(1 downto 0);
519  Block_B_pause : out std_logic_vector(1 downto 0)
520  );
521 END Component packet_status_block;
522 
523 COMPONENT SRLC32E is
524  generic(
525  INIT : std_logic_vector(31 downto 0) := (Others => '0')
526  );
527  port(
528  CLK : in std_logic;
529  D : in std_logic;
530  CE : in std_logic;
531  A : in std_logic_vector(4 downto 0);
532  Q : out std_logic;
533  Q31 : out std_logic
534  );
535 end COMPONENT SRLC32E;
536 
537  constant FPGA_mapping : STD_LOGIC_VECTOR (7 downto 0) := x"9C" ; -- HW address to processor number
538 
539  SIGNAL rst_320_sig, rst_320_end, rst_320_delay, l1a_enable_sig : std_logic;
540 
541 -- MGT input spy RAM IPBus
542  SIGNAL ipbus_tob_mgt_wbus_array, ipbus_raw_mgt_wbus_array : ipb_wbus_array(3 downto 0);
543  SIGNAL ipbus_tob_mgt_rbus_array, ipbus_raw_mgt_rbus_array : ipb_rbus_array(3 downto 0);
544 -- Aurora output and merger spy RAM IPBus
545  SIGNAL ipbus_merger_spy_wbus_array, ipbus_built_fifo_wbus_array : ipb_wbus_array(1 downto 0);
546  SIGNAL ipbus_merger_spy_rbus_array, ipbus_built_fifo_rbus_array : ipb_rbus_array(1 downto 0);
547 -- MGT TOB input spy RAM control
548  SIGNAL rst_ipbus_tob_mgt_addr_bus : std_logic_vector(3 downto 0);
549  SIGNAL ipbus_tob_mgt_wraparound_bus : std_logic_vector(3 downto 0);
550 -- MGT raw input spy RAM control
551  SIGNAL rst_ipbus_raw_mgt_addr_bus : std_logic_vector(3 downto 0);
552  SIGNAL ipbus_raw_mgt_wraparound_bus : std_logic_vector(3 downto 0);
553 -- Merger spy RAM control
554  SIGNAL rst_ipbus_merger_spy_addr_bus : std_logic_vector(1 downto 0);
555  SIGNAL ipbus_merger_spy_wraparound_bus : std_logic_vector(1 downto 0);
556 -- Aurora output spy RAM control
557  SIGNAL rst_ipbus_built_fifo_addr_bus : std_logic_vector(1 downto 0);
558  SIGNAL ipbus_built_fifo_wraparound_bus : std_logic_vector(1 downto 0);
559 -- Readout delay control
560  SIGNAL readout_delay : std_logic_vector(31 downto 0);
561 -- TOB blocks
562  SIGNAL tob_fifo_data_bus, tob_fifo_data_A_bus, tob_fifo_data_B_bus : packet_data_array(3 downto 0);
563  SIGNAL tob_fifo_last_bus, tob_fifo_last_A_bus, tob_fifo_last_B_bus : std_logic_vector(3 downto 0);
564  SIGNAL tob_fifo_valid_bus, tob_fifo_valid_A_bus, tob_fifo_valid_B_bus : std_logic_vector(3 downto 0);
565  SIGNAL tob_packet_data_A_bus, tob_packet_data_B_bus, tob_packet_data_A_reg_bus, tob_packet_data_B_reg_bus : packet_data_array(3 downto 0);
566  SIGNAL tob_packet_last_A_bus, tob_packet_last_B_bus, tob_packet_last_A_reg_bus, tob_packet_last_B_reg_bus : std_logic_vector(3 downto 0);
567  SIGNAL tob_packet_valid_A_bus, tob_packet_valid_B_bus, tob_packet_valid_A_reg_bus, tob_packet_valid_B_reg_bus : std_logic_vector(3 downto 0);
568  SIGNAL tob_packet_ready_A_bus, tob_packet_ready_B_bus, tob_packet_ready_A_reg_bus, tob_packet_ready_B_reg_bus : std_logic_vector(3 downto 0);
569  SIGNAL tob_fifo_reset_A_bus, tob_fifo_reset_B_bus : std_logic_vector(3 downto 0);
570  SIGNAL tob_fifo_fill_level_A_bus, tob_fifo_fill_level_B_bus : fifo_status_array(3 downto 0);
571  SIGNAL tob_packet_count_A_bus, tob_packet_count_B_bus : fifo_status_array(3 downto 0);
572  SIGNAL tob_fifo_empty_A_bus, tob_fifo_empty_B_bus, tob_input_error_A_bus, tob_input_error_B_bus, tob_fifo_error_A_bus, tob_fifo_error_B_bus : std_logic_vector(3 downto 0);
573  SIGNAL tob_mgt_packet_received_bus, tob_mgt_safe_mode_bus, tob_mgt_packet_err_bus, tob_mgt_length_err_bus, tob_mgt_bcn_err_bus: std_logic_vector(3 downto 0);
574  SIGNAL tob_mgt_last_l1id_bus: mgt_data_array(3 downto 0);
575 -- TTC FIFOs
576  SIGNAL ttc_dout_A, ttc_dout_B : std_logic_vector(49 DOWNTO 0);
577  SIGNAL ttc_empty_A, ttc_empty_B, ttc_rd_en_A, ttc_rd_en_B : std_logic;
578 -- TOB merging
579  SIGNAL TOB_Block_A_pause, TOB_Block_B_pause : std_logic_vector(1 downto 0);
580  SIGNAL merged_fifo_data_A_bus, merged_fifo_data_B_bus : packet_data_array(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1)
581  SIGNAL merged_fifo_last_A_bus, merged_fifo_last_B_bus : std_logic_vector(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1)
582  SIGNAL merged_fifo_valid_A_bus, merged_fifo_valid_B_bus : std_logic_vector(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1)
583  SIGNAL merged_fifo_fill_level_A_bus, merged_fifo_fill_level_B_bus : fifo_status_array(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1)
584  SIGNAL merged_packet_count_A_bus, merged_packet_count_B_bus : fifo_status_array(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1)
585  SIGNAL merged_input_error_A_bus, merged_input_error_B_bus : std_logic_vector(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1)
586  SIGNAL merged_fifo_error_A_bus, merged_fifo_error_B_bus : std_logic_vector(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1)
587  SIGNAL merged_fifo_reset_A_bus, merged_fifo_reset_B_bus : std_logic_vector(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1)
588  SIGNAL Last_L1ID_merger_A, Last_L1ID_merger_B : std_logic_vector(31 downto 0);
589  SIGNAL L1A_seen_bus : std_logic_vector(1 downto 0); -- Merger A (0), Merger B (1)
590  SIGNAL TOB_packet_merged_A_bus, TOB_packet_missing_A_bus, debug_packet_created_A_bus : std_logic_vector(3 downto 0);
591  SIGNAL TOB_packet_merged_B_bus, TOB_packet_missing_B_bus, debug_packet_created_B_bus : std_logic_vector(3 downto 0);
592 -- Raw blocks
593  SIGNAL raw_fifo_data_bus, raw_demux_data_bus, raw_fifo_data_A_bus, raw_fifo_data_B_bus : packet_data_array(3 downto 0);
594  SIGNAL raw_demux_pause_bus, raw_demux_pause_A_bus, raw_demux_pause_B_bus : std_logic_vector(3 downto 0);
595  SIGNAL raw_fifo_last_bus, raw_demux_last_bus, raw_fifo_last_A_bus, raw_fifo_last_B_bus : std_logic_vector(3 downto 0);
596  SIGNAL raw_fifo_valid_bus, raw_demux_valid_bus, raw_fifo_valid_A_bus, raw_fifo_valid_B_bus : std_logic_vector(3 downto 0);
597  SIGNAL raw_fifo_fill_level_bus : fifo_status_array(3 downto 0);
598  SIGNAL raw_packet_count_bus : fifo_status_array(3 downto 0);
599  SIGNAL raw_fifo_error_bus, raw_input_error_bus, raw_ram_fifo_error_bus, raw_fifo_error_A_bus, raw_fifo_error_B_bus, raw_fifo_reset_bus : std_logic_vector(3 downto 0);
600  SIGNAL raw_mgt_packet_received_bus, raw_mgt_safe_mode_bus, raw_mgt_packet_err_bus, raw_mgt_length_err_bus, raw_mgt_bcn_err_bus: std_logic_vector(3 downto 0);
601  SIGNAL raw_mgt_last_l1id_bus: mgt_data_array(3 downto 0);
602 -- MUX blocks
603  SIGNAL mux_data_A_bus, mux_data_B_bus : packet_data_array(5 downto 0); -- Raw(3 downto 0), Debug, TOB
604  SIGNAL mux_enable_A_bus, mux_enable_B_bus : std_logic_vector(5 downto 0); -- Raw(3 downto 0), Debug, TOB
605  SIGNAL mux_last_A_bus, mux_last_B_bus : std_logic_vector(5 downto 0); -- Raw(3 downto 0), Debug, TOB
606  SIGNAL mux_ready_A_bus, mux_ready_B_bus : std_logic_vector(5 downto 0); -- Raw(3 downto 0), Debug, TOB
607  SIGNAL mux_valid_A_bus, mux_valid_B_bus : std_logic_vector(5 downto 0); -- Raw(3 downto 0), Debug, TOB
608  SIGNAL mux_reset_A_bus, mux_reset_B_bus : std_logic_vector(5 downto 0); -- Raw(3 downto 0), Debug, TOB
609 -- MUX register blocks
610  SIGNAL mux_data_A_reg_bus, mux_data_B_reg_bus : packet_data_array(5 downto 0); -- Raw(3 downto 0), Debug, TOB
611  SIGNAL mux_last_A_reg_bus, mux_last_B_reg_bus : std_logic_vector(5 downto 0); -- Raw(3 downto 0), Debug, TOB
612  SIGNAL mux_ready_A_reg_bus, mux_ready_B_reg_bus : std_logic_vector(5 downto 0); -- Raw(3 downto 0), Debug, TOB
613  SIGNAL mux_valid_A_reg_bus, mux_valid_B_reg_bus : std_logic_vector(5 downto 0); -- Raw(3 downto 0), Debug, TOB
614 -- MUX monitoring signals
615  SIGNAL mux_active_bus, mux_l1id_valid_bus: std_logic_vector(1 downto 0);
616  SIGNAL mux_source_bus: std_logic_vector(7 downto 0);
617  SIGNAL mux_l1id_bus: mgt_data_array(1 downto 0);
618 -- Packet builder and output
619  SIGNAL packet_data_bus, packet_builder_data_bus, built_data_bus : packet_data_array(1 downto 0);
620  SIGNAL packet_last_bus, packet_valid_bus, packet_ready_bus, built_last_bus, built_valid_bus : std_logic_vector(1 downto 0);
621  SIGNAL packet_builder_last_bus, packet_builder_valid_bus, packet_builder_ready_bus : std_logic_vector(1 downto 0);
622 
623  SIGNAL source_enable_sig, raw_destination_select_sig : std_logic_vector(NProcessorFPGA*2 - 1 downto 0) := (Others => '0');
624  SIGNAL tob_destination_enable_sig : std_logic_vector(1 downto 0) := (Others => '0');
625 
626 -- BCR and ECR signals
627  SIGNAL bcr_40_tff, ecr_40_tff, bcr_320, ecr_320 : std_logic := '0';
628  SIGNAL bcr_320_tff_buf, ecr_320_tff_buf : std_logic_vector(1 downto 0) := (Others => '0');
629 
630  attribute ASYNC_REG : string;
631  attribute ASYNC_REG of bcr_320_tff_buf : signal is "TRUE";
632  attribute ASYNC_REG of ecr_320_tff_buf : signal is "TRUE";
633 
634 BEGIN
635 
636 TOB_sources: for i in 0 to NProcessorFPGA-1 generate
637 
638  MGT_object : mgt_buffer
639  GENERIC MAP (
640  INPUT_FPGA_NO => FPGA_mapping(i*2+1 downto i*2),
641  DATA_FORMAT_VERSION => "001",
642  IPBUS_ADDR_WIDTH => TOB_SPY_ADDR_WIDTH,
643  ILA_ENABLED => '1'
644  )
645  port map (
646 -- Static signals
647  eFEX_number => eFEX_number,
648  enable => source_enable_sig(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
649 -- data from MGT in U number order
650  clk_mgt => clk_mgt_bus(i*2),
651  data_from_mgt => data_from_mgt_bus(i*2),
652  char_is_k => char_is_k_bus(i*2),
653  error_from_mgt => error_from_mgt_bus(i*2),
654 -- data to fifo blocks in Processor FPGA Number order
655  clk_320 => clk_320,
656  rst_320 => rst_320_sig,
657  fifo_data => tob_fifo_data_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
658  fifo_valid => tob_fifo_valid_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
659  fifo_last => tob_fifo_last_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
660 -- status
661  mgt_last_l1id => tob_mgt_last_l1id_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
662  mgt_packet_stats(4) => tob_mgt_safe_mode_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
663  mgt_packet_stats(3) => tob_mgt_packet_err_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
664  mgt_packet_stats(2) => tob_mgt_length_err_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
665  mgt_packet_stats(1) => tob_mgt_bcn_err_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
666  mgt_packet_stats(0) => tob_mgt_packet_received_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
667 -- interface to IPBus for spy RAM
668  clk_ipb => clk_ipb,
669  rst_ipb => rst_ipb,
670  rst_ipbus_addr => rst_ipbus_tob_mgt_addr_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
671  ipbus_wraparound => ipbus_tob_mgt_wraparound_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
672  ipb_in => ipbus_tob_mgt_wbus_array(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
673  ipb_out => ipbus_tob_mgt_rbus_array(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2))))
674  );
675 
676  tob_fifo_selector : fifo_selector
677  port map (
678  clk_320 => clk_320,
679 -- FIFO data from MGT block
680  fifo_data => tob_fifo_data_bus(i),
681  fifo_valid => tob_fifo_valid_bus(i),
682  fifo_last => tob_fifo_last_bus(i),
683 -- data to FIFO A
684  fifo_data_A => tob_fifo_data_A_bus(i),
685  fifo_valid_A => tob_fifo_valid_A_bus(i),
686  fifo_last_A => tob_fifo_last_A_bus(i),
687 -- data to FIFO B
688  fifo_data_B => tob_fifo_data_B_bus(i),
689  fifo_valid_B => tob_fifo_valid_B_bus(i),
690  fifo_last_B => tob_fifo_last_B_bus(i),
691  destination_enable => tob_destination_enable_sig
692  );
693 
694  tob_fifo_A : packet_fifo_block
695  GENERIC MAP (
696  RAM_ADDR_WIDTH => TOB_FIFO_ADDR_WIDTH,
697  MAX_PACKET_WIDTH => MAX_BUILT_PACKET_WIDTH
698  )
699  port map (
700  clk_320 => clk_320,
701  rst_320 => tob_fifo_reset_A_bus(i),
702 --
703  fifo_data => tob_fifo_data_A_bus(i),
704  fifo_valid => tob_fifo_valid_A_bus(i),
705  fifo_last => tob_fifo_last_A_bus(i),
706 --
707  packet_data => tob_packet_data_A_bus(i),
708  packet_valid => tob_packet_valid_A_bus(i),
709  packet_last => tob_packet_last_A_bus(i),
710  packet_ready => tob_packet_ready_A_bus(i),
711 --
712  fifo_fill_level => tob_fifo_fill_level_A_bus(i),
713  packet_count => tob_packet_count_A_bus(i),
714  fifo_empty => tob_fifo_empty_A_bus(i),
715  input_error => tob_input_error_A_bus(i),
716  fifo_error => tob_fifo_error_A_bus(i)
717  );
718 
719  TOB_register_A : fwft_register
720  GENERIC MAP (
721  DATA_WIDTH => 65 -- DATA bus width + 1
722  )
723  port map (
724  clk => clk_320,
725  rst_clk => tob_fifo_reset_A_bus(i),
726  -- Input signals
727  in_data(63 downto 0) => tob_packet_data_A_bus(i),
728  in_data(64) => tob_packet_last_A_bus(i),
729  in_valid => tob_packet_valid_A_bus(i),
730  in_ready => tob_packet_ready_A_bus(i),
731  -- Output signals
732  out_data(63 downto 0) => tob_packet_data_A_reg_bus(i),
733  out_data(64) => tob_packet_last_A_reg_bus(i),
734  out_valid => tob_packet_valid_A_reg_bus(i),
735  out_ready => tob_packet_ready_A_reg_bus(i)
736  );
737 
738  tob_fifo_reset_A : packet_fifo_reset_block
739  Port map (
740  clk => clk_320,
741  rst => rst_320_sig,
742  fifo_valid => tob_fifo_valid_A_bus(i),
743  fifo_last => tob_fifo_last_A_bus(i),
744  fifo_error => tob_fifo_error_A_bus(i),
745  fifo_reset => tob_fifo_reset_A_bus(i)
746  );
747 
748  tob_fifo_B : packet_fifo_block
749  generic map (
750  RAM_ADDR_WIDTH => TOB_FIFO_ADDR_WIDTH,
751  MAX_PACKET_WIDTH => MAX_BUILT_PACKET_WIDTH
752  )
753  port map (
754  clk_320 => clk_320,
755  rst_320 => tob_fifo_reset_B_bus(i),
756 --
757  fifo_data => tob_fifo_data_B_bus(i),
758  fifo_valid => tob_fifo_valid_B_bus(i),
759  fifo_last => tob_fifo_last_B_bus(i),
760 --
761  packet_data => tob_packet_data_B_bus(i),
762  packet_valid => tob_packet_valid_B_bus(i),
763  packet_last => tob_packet_last_B_bus(i),
764  packet_ready => tob_packet_ready_B_bus(i),
765 --
766  fifo_fill_level => tob_fifo_fill_level_B_bus(i),
767  packet_count => tob_packet_count_B_bus(i),
768  fifo_empty => tob_fifo_empty_B_bus(i),
769  input_error => tob_input_error_B_bus(i),
770  fifo_error => tob_fifo_error_B_bus(i)
771  );
772 
773  TOB_register_B : fwft_register
774  GENERIC MAP (
775  DATA_WIDTH => 65 -- DATA bus width + 1
776  )
777  port map (
778  clk => clk_320,
779  rst_clk => tob_fifo_reset_B_bus(i),
780  -- Input signals
781  in_data(63 downto 0) => tob_packet_data_B_bus(i),
782  in_data(64) => tob_packet_last_B_bus(i),
783  in_valid => tob_packet_valid_B_bus(i),
784  in_ready => tob_packet_ready_B_bus(i),
785  -- Output signals
786  out_data(63 downto 0) => tob_packet_data_B_reg_bus(i),
787  out_data(64) => tob_packet_last_B_reg_bus(i),
788  out_valid => tob_packet_valid_B_reg_bus(i),
789  out_ready => tob_packet_ready_B_reg_bus(i)
790  );
791 
792  tob_fifo_reset_B : packet_fifo_reset_block
793  Port map (
794  clk => clk_320,
795  rst => rst_320_sig,
796  fifo_valid => tob_fifo_valid_B_bus(i),
797  fifo_last => tob_fifo_last_B_bus(i),
798  fifo_error => tob_fifo_error_B_bus(i),
799  fifo_reset => tob_fifo_reset_B_bus(i)
800  );
801 
802  End generate TOB_sources;
803 
804 ttc_fifos : ttc_fifo_block
805  generic map (
806  DELAY_DEPTH => 63 -- Number of SRLC32E to cascade for delayed L1A strobe in 40 MHz clock domain
807  )
808  port map (
809 -- clocks etc
810  clk40 => clk40,
811  clk_320 => clk_320,
812 -- TTC input FIFO
813  rst_ttc => rst_ttc,
814  ttc_wr_en => ttc_wr_en,
815  ttc_rd_en => ttc_rd_en,
816  ttc_din => ttc_din,
817 -- TTC output FIFOs
818  ttc_rd_en_A => ttc_rd_en_A,
819  ttc_empty_A => ttc_empty_A,
820  ttc_dout_A => ttc_dout_A,
821  ttc_rd_en_B => ttc_rd_en_B,
822  ttc_empty_B => ttc_empty_B,
823  ttc_dout_B => ttc_dout_B,
824 -- input and output control
825  destination_enable => tob_destination_enable_sig,
826  readout_delay => readout_delay(7 downto 0)
827  );
828 
829 tob_merge_A : efex_tob_merger
830  GENERIC map (
831  DATA_FORMAT_VERSION => "001"
832  )
833  port map (
834  clk => clk_320,
835  rst_clk => rst_320_sig,
836  eFEX_number => eFEX_number,
837 -- Control signals
838  ifg_duration => readout_delay(11 downto 8),
839  fpga_tob_enabled => source_enable_sig(3 downto 0), -- Processor Number order, TOBs first
840  pause => TOB_Block_A_pause,
841 -- TTC FIFO signals
842  ttc_rd_en => ttc_rd_en_A,
843  ttc_dout => ttc_dout_A,
844  ttc_fifo_empty => ttc_empty_A,
845 -- Input pFPGA TOB packets
846  input_fifo_empty => tob_fifo_empty_A_bus,
847  fpga_tob_data => tob_packet_data_A_reg_bus,
848  fpga_tob_valid => tob_packet_valid_A_reg_bus,
849  fpga_tob_last => tob_packet_last_A_reg_bus,
850  fpga_tob_ready => tob_packet_ready_A_reg_bus,
851 -- Output FIFO signals
852  merged_fifo_data => merged_fifo_data_A_bus,
853  merged_fifo_valid => merged_fifo_valid_A_bus,
854  merged_fifo_last => merged_fifo_last_A_bus,
855 -- Status signals
856  L1A_seen => L1A_seen_bus(0),
857  Last_L1ID_merged => Last_L1ID_merger_A,
858  TOB_packet_merged_bus => TOB_packet_merged_A_bus,
859  TOB_packet_missing_bus => TOB_packet_missing_A_bus,
860  debug_packet_created_bus => debug_packet_created_A_bus
861  );
862 
863 tob_spy_A: tob_merger_spy
864  Generic map (RAM_ADDR_WIDTH => MERGER_SPY_ADDR_WIDTH)
865  port map (
866  clk_320 => clk_320,
867  rst_320 => rst_320_sig,
868 -- TOB MGT status signals
869  tob_mgt_packet_err_bus => tob_mgt_packet_err_bus,
870  tob_mgt_length_err_bus => tob_mgt_length_err_bus,
871  tob_mgt_last_l1id_bus => tob_mgt_last_l1id_bus,
872 -- Merger status signals
873  L1A_seen => L1A_seen_bus(0),
874  Last_L1ID_merged => Last_L1ID_merger_A,
875 -- Merger output FIFO signals
876  merged_fifo_data => merged_fifo_data_A_bus,
877  merged_fifo_valid => merged_fifo_valid_A_bus,
878  merged_fifo_last => merged_fifo_last_A_bus,
879 -- interface to IPBus
880  clk_ipb => clk_ipb,
881  rst_ipb => rst_ipb,
882  rst_ipbus_addr => rst_ipbus_merger_spy_addr_bus(0),
883  ipbus_wraparound => ipbus_merger_spy_wraparound_bus(0),
884  ipb_in => ipbus_merger_spy_wbus_array(0),
885  ipb_out => ipbus_merger_spy_rbus_array(0)
886  );
887 
888 tob_merge_B : efex_tob_merger
889  GENERIC map (
890  DATA_FORMAT_VERSION => "001"
891  )
892  port map (
893  clk => clk_320,
894  rst_clk => rst_320_sig,
895  eFEX_number => eFEX_number,
896 -- Control signals
897  ifg_duration => readout_delay(11 downto 8),
898  fpga_tob_enabled => source_enable_sig(3 downto 0), -- Processor Number order, TOBs first
899  pause => TOB_Block_B_pause,
900 -- TTC FIFO signals
901  ttc_rd_en => ttc_rd_en_B,
902  ttc_dout => ttc_dout_B,
903  ttc_fifo_empty => ttc_empty_B,
904 -- Input pFPGA TOB packets
905  input_fifo_empty => tob_fifo_empty_B_bus,
906  fpga_tob_data => tob_packet_data_B_reg_bus,
907  fpga_tob_valid => tob_packet_valid_B_reg_bus,
908  fpga_tob_last => tob_packet_last_B_reg_bus,
909  fpga_tob_ready => tob_packet_ready_B_reg_bus,
910 -- Output FIFO signals
911  merged_fifo_data => merged_fifo_data_B_bus,
912  merged_fifo_valid => merged_fifo_valid_B_bus,
913  merged_fifo_last => merged_fifo_last_B_bus,
914 -- Status signals
915  L1A_seen => L1A_seen_bus(1),
916  Last_L1ID_merged => Last_L1ID_merger_B,
917  TOB_packet_merged_bus => TOB_packet_merged_B_bus,
918  TOB_packet_missing_bus => TOB_packet_missing_B_bus,
919  debug_packet_created_bus => debug_packet_created_B_bus
920  );
921 
922 tob_spy_B: tob_merger_spy
923  Generic map (RAM_ADDR_WIDTH => MERGER_SPY_ADDR_WIDTH)
924  port map (
925  clk_320 => clk_320,
926  rst_320 => rst_320_sig,
927 -- TOB MGT status signals
928  tob_mgt_packet_err_bus => tob_mgt_packet_err_bus,
929  tob_mgt_length_err_bus => tob_mgt_length_err_bus,
930  tob_mgt_last_l1id_bus => tob_mgt_last_l1id_bus,
931 -- Merger status signals
932  L1A_seen => L1A_seen_bus(1),
933  Last_L1ID_merged => Last_L1ID_merger_B,
934 -- Merger output FIFO signals
935  merged_fifo_data => merged_fifo_data_B_bus,
936  merged_fifo_valid => merged_fifo_valid_B_bus,
937  merged_fifo_last => merged_fifo_last_B_bus,
938 -- interface to IPBus
939  clk_ipb => clk_ipb,
940  rst_ipb => rst_ipb,
941  rst_ipbus_addr => rst_ipbus_merger_spy_addr_bus(1),
942  ipbus_wraparound => ipbus_merger_spy_wraparound_bus(1),
943  ipb_in => ipbus_merger_spy_wbus_array(1),
944  ipb_out => ipbus_merger_spy_rbus_array(1)
945  );
946 
947 Merged_FIFOs: for i in 0 to 1 generate
948  merged_fifo_A : packet_fifo_block
949  GENERIC MAP (
950  RAM_ADDR_WIDTH => MERGED_FIFO_ADDR_WIDTH,
951  MAX_PACKET_WIDTH => MAX_BUILT_PACKET_WIDTH+2
952  )
953  port map (
954  clk_320 => clk_320,
955  rst_320 => merged_fifo_reset_A_bus(i),
956 --
957  fifo_data => merged_fifo_data_A_bus(i),
958  fifo_valid => merged_fifo_valid_A_bus(i),
959  fifo_last => merged_fifo_last_A_bus(i),
960 --
961  packet_data => mux_data_A_bus(i),
962  packet_valid => mux_valid_A_bus(i),
963  packet_last => mux_last_A_bus(i),
964  packet_ready => mux_ready_A_bus(i),
965 --
966  fifo_fill_level => merged_fifo_fill_level_A_bus(i),
967  packet_count => merged_packet_count_A_bus(i),
968  fifo_empty => OPEN,
969  input_error => merged_input_error_A_bus(i),
970  fifo_error => merged_fifo_error_A_bus(i)
971  );
972 
973  merged_fifo_reset_block_A: packet_fifo_reset_block
974  Port map (
975  clk => clk_320,
976  rst => rst_320_sig,
977  fifo_valid => merged_fifo_valid_A_bus(i),
978  fifo_last => merged_fifo_last_A_bus(i),
979  fifo_error => merged_fifo_error_A_bus(i),
980  fifo_reset => merged_fifo_reset_A_bus(i)
981  );
982 
983  merged_fifo_B : packet_fifo_block
984  GENERIC MAP (
985  RAM_ADDR_WIDTH => MERGED_FIFO_ADDR_WIDTH,
986  MAX_PACKET_WIDTH => MAX_BUILT_PACKET_WIDTH+2
987  )
988  port map (
989  clk_320 => clk_320,
990  rst_320 => merged_fifo_reset_B_bus(i),
991 --
992  fifo_data => merged_fifo_data_B_bus(i),
993  fifo_valid => merged_fifo_valid_B_bus(i),
994  fifo_last => merged_fifo_last_B_bus(i),
995 --
996  packet_data => mux_data_B_bus(i),
997  packet_valid => mux_valid_B_bus(i),
998  packet_last => mux_last_B_bus(i),
999  packet_ready => mux_ready_B_bus(i),
1000 --
1001  fifo_fill_level => merged_fifo_fill_level_B_bus(i),
1002  packet_count => merged_packet_count_B_bus(i),
1003  fifo_empty => OPEN,
1004  input_error => merged_input_error_B_bus(i),
1005  fifo_error => merged_fifo_error_B_bus(i)
1006  );
1007 
1008  merged_fifo_reset_block_B: packet_fifo_reset_block
1009  Port map (
1010  clk => clk_320,
1011  rst => rst_320_sig,
1012  fifo_valid => merged_fifo_valid_B_bus(i),
1013  fifo_last => merged_fifo_last_B_bus(i),
1014  fifo_error => merged_fifo_error_B_bus(i),
1015  fifo_reset => merged_fifo_reset_B_bus(i)
1016  );
1017 
1018  End generate Merged_FIFOs;
1019 
1020 Bulk_sources: for i in 0 to NProcessorFPGA-1 generate
1021  MGT_object : mgt_buffer
1022  GENERIC MAP (
1023  INPUT_FPGA_NO => FPGA_mapping(i*2+1 downto i*2),
1024  DATA_FORMAT_VERSION => "001",
1025  IPBUS_ADDR_WIDTH => RAW_SPY_ADDR_WIDTH,
1026  ILA_ENABLED => '0'
1027  )
1028  port map (
1029 -- Static signals
1030  eFEX_number => eFEX_number,
1031  enable => source_enable_sig(NProcessorFPGA+to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
1032 -- data from MGT in U number order
1033  clk_mgt => clk_mgt_bus(i*2+1),
1034  data_from_mgt => data_from_mgt_bus(i*2+1),
1035  char_is_k => char_is_k_bus(i*2+1),
1036  error_from_mgt => error_from_mgt_bus(i*2+1),
1037 -- data to fifo blocks in Processor FPGA Number order
1038  clk_320 => clk_320,
1039  rst_320 => rst_320_sig,
1040  fifo_data => raw_fifo_data_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
1041  fifo_valid => raw_fifo_valid_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
1042  fifo_last => raw_fifo_last_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
1043 -- status (N.B. no BCN errors for Input Data)
1044  mgt_last_l1id => raw_mgt_last_l1id_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
1045  mgt_packet_stats(4) => raw_mgt_safe_mode_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
1046  mgt_packet_stats(3) => raw_mgt_packet_err_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
1047  mgt_packet_stats(2) => raw_mgt_length_err_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
1048  mgt_packet_stats(1) => raw_mgt_bcn_err_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
1049  mgt_packet_stats(0) => raw_mgt_packet_received_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
1050 -- interface to IPBus
1051  clk_ipb => clk_ipb,
1052  rst_ipb => rst_ipb,
1053  rst_ipbus_addr => rst_ipbus_raw_mgt_addr_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
1054  ipbus_wraparound => ipbus_raw_mgt_wraparound_bus(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
1055  ipb_in => ipbus_raw_mgt_wbus_array(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2)))),
1056  ipb_out => ipbus_raw_mgt_rbus_array(to_integer(unsigned(FPGA_mapping(i*2+1 downto i*2))))
1057  );
1058 
1059  raw_ram_fifo : packet_ram_fifo
1060  GENERIC MAP (
1061  DATA_WIDTH => 64,
1062  BUFWIDTH => RAW_FIFO_ADDR_WIDTH,
1063  MAXWIDTH => 8
1064  )
1065  port map (
1066  clk => clk_320,
1067  rst_clk => raw_fifo_reset_bus(i),
1068 -- Data now in Processor FPGA Number order
1069  in_data => raw_fifo_data_bus(i),
1070  in_valid => raw_fifo_valid_bus(i),
1071  in_last => raw_fifo_last_bus(i),
1072 --
1073  out_data => raw_demux_data_bus(i),
1074  out_valid => raw_demux_valid_bus(i),
1075  out_last => raw_demux_last_bus(i),
1076  out_pause => raw_demux_pause_bus(i),
1077 --
1078  fifo_fill_level => raw_fifo_fill_level_bus(i),
1079  packet_count => raw_packet_count_bus(i),
1080  in_error => raw_input_error_bus(i),
1081  out_error => raw_ram_fifo_error_bus(i)
1082  );
1083 
1084  raw_fifo_selector : fifo_selector
1085  port map (
1086  clk_320 => clk_320,
1087 -- FIFO data from MGT block
1088  fifo_data => raw_demux_data_bus(i),
1089  fifo_valid => raw_demux_valid_bus(i),
1090  fifo_last => raw_demux_last_bus(i),
1091 -- data to FIFO A
1092  fifo_data_A => raw_fifo_data_A_bus(i),
1093  fifo_valid_A => raw_fifo_valid_A_bus(i),
1094  fifo_last_A => raw_fifo_last_A_bus(i),
1095 -- data to FIFO B
1096  fifo_data_B => raw_fifo_data_B_bus(i),
1097  fifo_valid_B => raw_fifo_valid_B_bus(i),
1098  fifo_last_B => raw_fifo_last_B_bus(i),
1099  destination_enable => raw_destination_select_sig(i*2+1 downto i*2)
1100  );
1101 
1102  raw_fifo_A : packet_fifo
1103  GENERIC MAP (
1104  DATA_WIDTH => 64,
1105  BUFWIDTH => 4
1106  )
1107  port map (
1108  clk => clk_320,
1109  rst_clk => raw_fifo_reset_bus(i),
1110 --
1111  in_data => raw_fifo_data_A_bus(i),
1112  in_valid => raw_fifo_valid_A_bus(i),
1113  in_last => raw_fifo_last_A_bus(i),
1114  in_pause => raw_demux_pause_A_bus(i),
1115 --
1116  out_data => mux_data_A_bus(i+2),
1117  out_valid => mux_valid_A_bus(i+2),
1118  out_last => mux_last_A_bus(i+2),
1119  out_ready => mux_ready_A_bus(i+2),
1120  out_error => raw_fifo_error_A_bus(i)
1121  );
1122 
1123  raw_fifo_B : packet_fifo
1124  GENERIC MAP (
1125  DATA_WIDTH => 64,
1126  BUFWIDTH => 4
1127  )
1128  port map (
1129  clk => clk_320,
1130  rst_clk => raw_fifo_reset_bus(i),
1131 --
1132  in_data => raw_fifo_data_B_bus(i),
1133  in_valid => raw_fifo_valid_B_bus(i),
1134  in_last => raw_fifo_last_B_bus(i),
1135  in_pause => raw_demux_pause_B_bus(i),
1136 --
1137  out_data => mux_data_B_bus(i+2),
1138  out_valid => mux_valid_B_bus(i+2),
1139  out_last => mux_last_B_bus(i+2),
1140  out_ready => mux_ready_B_bus(i+2),
1141  out_error => raw_fifo_error_B_bus(i)
1142  );
1143 
1144  raw_fifo_reset_block: packet_fifo_reset_block
1145  Port map (
1146  clk => clk_320,
1147  rst => rst_320_sig,
1148  fifo_valid => raw_fifo_valid_bus(i),
1149  fifo_last => raw_fifo_last_bus(i),
1150  fifo_error => raw_fifo_error_bus(i),
1151  fifo_reset => raw_fifo_reset_bus(i)
1152  );
1153 
1154  End generate Bulk_sources;
1155 
1156  raw_demux_pause_bus <= raw_demux_pause_A_bus or raw_demux_pause_B_bus;
1157  raw_fifo_error_bus <= raw_ram_fifo_error_bus or raw_fifo_error_A_bus or raw_fifo_error_B_bus;
1158 
1159  mux_reset_A_bus <= raw_fifo_reset_bus & merged_fifo_reset_A_bus;
1160  mux_reset_B_bus <= raw_fifo_reset_bus & merged_fifo_reset_B_bus;
1161 
1162 MUX_registers: for i in 0 to 5 generate
1163  MUX_register_A : fwft_register
1164  GENERIC MAP (
1165  DATA_WIDTH => 65 -- DATA bus width + 1
1166  )
1167  port map (
1168  clk => clk_320,
1169  rst_clk => mux_reset_A_bus(i),
1170  -- Input signals
1171  in_data(63 downto 0) => mux_data_A_bus(i),
1172  in_data(64) => mux_last_A_bus(i),
1173  in_valid => mux_valid_A_bus(i),
1174  in_ready => mux_ready_A_bus(i),
1175  -- Output signals
1176  out_data(63 downto 0) => mux_data_A_reg_bus(i),
1177  out_data(64) => mux_last_A_reg_bus(i),
1178  out_valid => mux_valid_A_reg_bus(i),
1179  out_ready => mux_ready_A_reg_bus(i)
1180  );
1181 
1182  MUX_register_B : fwft_register
1183  GENERIC MAP (
1184  DATA_WIDTH => 65 -- DATA bus width + 1
1185  )
1186  port map (
1187  clk => clk_320,
1188  rst_clk => mux_reset_B_bus(i),
1189  -- Input signals
1190  in_data(63 downto 0) => mux_data_B_bus(i),
1191  in_data(64) => mux_last_B_bus(i),
1192  in_valid => mux_valid_B_bus(i),
1193  in_ready => mux_ready_B_bus(i),
1194  -- Output signals
1195  out_data(63 downto 0) => mux_data_B_reg_bus(i),
1196  out_data(64) => mux_last_B_reg_bus(i),
1197  out_valid => mux_valid_B_reg_bus(i),
1198  out_ready => mux_ready_B_reg_bus(i)
1199  );
1200 
1201  End generate MUX_registers;
1202 
1203 Packet_MUX_A : efex_packet_mux
1204  GENERIC MAP (
1205  NSRC => 6
1206  )
1207  PORT MAP (
1208  clk => clk_320,
1209  rst_clk => rst_320_sig,
1210  eFEX_number => eFEX_number,
1211  pause => '0',
1212  packet_mux_enabled => mux_enable_A_bus,
1213  packet_mux_reset => mux_reset_A_bus,
1214  packet_mux_source => mux_source_bus(3 downto 0),
1215  packet_mux_data => mux_data_A_reg_bus,
1216  packet_mux_valid => mux_valid_A_reg_bus,
1217  packet_mux_last => mux_last_A_reg_bus,
1218  packet_mux_ready => mux_ready_A_reg_bus,
1219  packet_data => packet_data_bus(0),
1220  packet_valid => packet_valid_bus(0),
1221  packet_last => packet_last_bus(0),
1222  packet_ready => packet_ready_bus(0)
1223  );
1224 
1225 Packet_MUX_B : efex_packet_mux
1226  GENERIC MAP (
1227  NSRC => 6
1228  )
1229  PORT MAP (
1230  clk => clk_320,
1231  rst_clk => rst_320_sig,
1232  eFEX_number => eFEX_number,
1233  pause => '0',
1234  packet_mux_enabled => mux_enable_B_bus,
1235  packet_mux_reset => mux_reset_B_bus,
1236  packet_mux_source => mux_source_bus(7 downto 4),
1237  packet_mux_data => mux_data_B_reg_bus,
1238  packet_mux_valid => mux_valid_B_reg_bus,
1239  packet_mux_last => mux_last_B_reg_bus,
1240  packet_mux_ready => mux_ready_B_reg_bus,
1241  packet_data => packet_data_bus(1),
1242  packet_valid => packet_valid_bus(1),
1243  packet_last => packet_last_bus(1),
1244  packet_ready => packet_ready_bus(1)
1245  );
1246 
1247  packet_mux_source <= mux_source_bus;
1248 
1249 MUX_monitor_block: process(clk_320)
1250  Variable mux_active_var, mux_l1id_valid_var: std_logic_vector(1 downto 0) := (Others => '0');
1251  Variable mux_l1id_var: mgt_data_array(1 downto 0) := (Others => (Others => '0'));
1252  begin
1253  if rising_edge(clk_320) then
1254  if (rst_320_sig = '1') then
1255  mux_active_var := (Others => '0');
1256  mux_l1id_valid_var := (Others => '0');
1257  mux_l1id_var := (Others => (Others => '0'));
1258  else
1259  for i in 0 to 1 loop
1260  if (mux_active_var(i) = '0') and (packet_valid_bus(i) = '1') then -- activate and sample L1ID of new packet
1261  mux_l1id_valid_var(i) := '1';
1262  mux_l1id_var(i) := packet_data_bus(i)(63 downto 32);
1263  mux_active_var(i) := '1';
1264  else
1265  mux_l1id_valid_var(i) := '0';
1266  mux_l1id_var(i) := (Others => '0');
1267  end if;
1268  if (packet_last_bus(i) = '1') and (packet_valid_bus(i) = '1') and (packet_ready_bus(i) = '1') then -- end of packet
1269  mux_active_var(i) := '0';
1270  end if;
1271  end loop;
1272  end if;
1273  mux_active_bus <= mux_active_var
1274 -- pragma translate_off
1275  after 2 ns
1276 -- pragma translate_on
1277  ;
1278  mux_l1id_valid_bus <= mux_l1id_valid_var
1279 -- pragma translate_off
1280  after 2 ns
1281 -- pragma translate_on
1282  ;
1283  mux_l1id_bus <= mux_l1id_var
1284 -- pragma translate_off
1285  after 2 ns
1286 -- pragma translate_on
1287  ;
1288  end if;
1289  end process MUX_monitor_block;
1290 
1291 Packet_builders: for i in 0 to 1 generate
1292  Packet_Builder_register : fwft_register
1293  GENERIC MAP (
1294  DATA_WIDTH => 65 -- DATA bus width + 1
1295  )
1296  port map (
1297  clk => clk_320,
1298  rst_clk => rst_320_sig,
1299  -- Input signals
1300  in_data(63 downto 0) => packet_data_bus(i),
1301  in_data(64) => packet_last_bus(i),
1302  in_valid => packet_valid_bus(i),
1303  in_ready => packet_ready_bus(i),
1304  -- Output signals
1305  out_data(63 downto 0) => packet_builder_data_bus(i),
1306  out_data(64) => packet_builder_last_bus(i),
1307  out_valid => packet_builder_valid_bus(i),
1308  out_ready => packet_builder_ready_bus(i)
1309  );
1310 
1311  Packet_Builder : efex_packet_builder
1312  PORT MAP (
1313  clk => clk_320,
1314  rst_clk => rst_320_sig,
1315  packet_data => packet_builder_data_bus(i),
1316  packet_valid => packet_builder_valid_bus(i),
1317  packet_last => packet_builder_last_bus(i),
1318  packet_ready => packet_builder_ready_bus(i),
1319  payload_data => built_data_bus(i),
1320  payload_valid => built_valid_bus(i),
1321  payload_last => built_last_bus(i),
1322  tready_data => tready_data_bus(i)
1323  );
1324 
1325  built_fifo_spy : fifo_spy
1326  GENERIC map (
1327  IPBUS_ADDR_WIDTH => AURORA_SPY_ADDR_WIDTH
1328  )
1329  port map (
1330  --- data to FIFO
1331  clk_320 => clk_320,
1332  rst_320 => rst_320_sig,
1333  fifo_data => built_data_bus(i),
1334  fifo_valid => built_valid_bus(i),
1335  fifo_last => built_last_bus(i),
1336  fifo_tready => tready_data_bus(i),
1337  -- interface to IPBus
1338 -- interface to IPBus for spy RAM
1339  clk_ipb => clk_ipb,
1340  rst_ipb => rst_ipb,
1341  rst_ipbus_addr => rst_ipbus_built_fifo_addr_bus(i),
1342  ipbus_wraparound => ipbus_built_fifo_wraparound_bus(i),
1343  ipb_in => ipbus_built_fifo_wbus_array(i),
1344  ipb_out => ipbus_built_fifo_rbus_array(i)
1345  );
1346 
1347  End generate Packet_builders;
1348 
1349  payload_data_bus <= built_data_bus;
1350  payload_valid_bus <= built_valid_bus;
1351  payload_last_bus <= built_last_bus;
1352 
1353 IPBusblock : packet_status_block
1354  GENERIC map (
1355  TOB_FIFO_ADDR_MAX_WIDTH => TOB_FIFO_ADDR_WIDTH,
1356  MERGED_FIFO_ADDR_MAX_WIDTH => MERGED_FIFO_ADDR_WIDTH,
1357  RAW_FIFO_ADDR_MAX_WIDTH => RAW_FIFO_ADDR_WIDTH,
1358  MAX_PACKET_WIDTH => MAX_BUILT_PACKET_WIDTH
1359  )
1360  port map (
1361 -- clocks etc
1362  clk_320 => clk_320,
1363  clk_ipb => clk_ipb,
1364  rst_320 => rst_320_sig,
1365  rst_ipb => rst_ipb,
1366  bcr_320 => bcr_320,
1367  ecr_320 => ecr_320,
1368 -- upstream IPBus
1369  ipb_in => ipb_in,
1370  ipb_out => ipb_out,
1371 -- MGT TOB input spy RAMs
1372  ipbus_tob_mgt_wbus_array => ipbus_tob_mgt_wbus_array,
1373  ipbus_tob_mgt_rbus_array => ipbus_tob_mgt_rbus_array,
1374 -- MGT raw input spy RAMs
1375  ipbus_raw_mgt_wbus_array => ipbus_raw_mgt_wbus_array,
1376  ipbus_raw_mgt_rbus_array => ipbus_raw_mgt_rbus_array,
1377 -- Merger debug spy RAMs
1378  ipbus_merger_spy_wbus_array => ipbus_merger_spy_wbus_array,
1379  ipbus_merger_spy_rbus_array => ipbus_merger_spy_rbus_array,
1380 -- Aurora output spy RAMs
1381  ipbus_built_fifo_wbus_array => ipbus_built_fifo_wbus_array,
1382  ipbus_built_fifo_rbus_array => ipbus_built_fifo_rbus_array,
1383 -- MGT TOB input spy RAM control
1384  rst_ipbus_tob_mgt_addr_bus => rst_ipbus_tob_mgt_addr_bus,
1385  ipbus_tob_mgt_wraparound_bus => ipbus_tob_mgt_wraparound_bus,
1386 -- MGT raw input spy RAM control
1387  rst_ipbus_raw_mgt_addr_bus => rst_ipbus_raw_mgt_addr_bus,
1388  ipbus_raw_mgt_wraparound_bus => ipbus_raw_mgt_wraparound_bus,
1389 -- Merger debug spy RAM control
1390  rst_ipbus_merger_spy_addr_bus => rst_ipbus_merger_spy_addr_bus,
1391  ipbus_merger_spy_wraparound_bus => ipbus_merger_spy_wraparound_bus,
1392 -- Aurora output spy RAM control
1393  rst_ipbus_built_fifo_addr_bus => rst_ipbus_built_fifo_addr_bus,
1394  ipbus_built_fifo_wraparound_bus => ipbus_built_fifo_wraparound_bus,
1395 -- Readout delay control
1396  readout_delay => readout_delay,
1397 -- L1A status
1398  L1A_seen_bus => L1A_seen_bus,
1399  Last_L1ID_merger_A => Last_L1ID_merger_A,
1400  Last_L1ID_merger_B => Last_L1ID_merger_B,
1401 -- TOB MGT status
1402  tob_mgt_packet_received_bus => tob_mgt_packet_received_bus,
1403  tob_mgt_safe_mode_bus => tob_mgt_safe_mode_bus,
1404  tob_mgt_packet_err_bus => tob_mgt_packet_err_bus,
1405  tob_mgt_length_err_bus => tob_mgt_length_err_bus,
1406  tob_mgt_bcn_err_bus => tob_mgt_bcn_err_bus,
1407  tob_mgt_last_l1id_bus => tob_mgt_last_l1id_bus,
1408 -- Raw MGT status
1409  raw_mgt_packet_received_bus => raw_mgt_packet_received_bus,
1410  raw_mgt_safe_mode_bus => raw_mgt_safe_mode_bus,
1411  raw_mgt_packet_err_bus => raw_mgt_packet_err_bus,
1412  raw_mgt_length_err_bus => raw_mgt_length_err_bus,
1413  raw_mgt_last_l1id_bus => raw_mgt_last_l1id_bus,
1414 -- TOB FIFO status block A
1415  tob_fifo_fill_level_A_bus => tob_fifo_fill_level_A_bus,
1416  tob_packet_count_A_bus => tob_packet_count_A_bus,
1417  tob_fifo_error_A_bus => tob_fifo_error_A_bus,
1418  merged_fifo_fill_level_A_bus => merged_fifo_fill_level_A_bus,
1419  merged_packet_count_A_bus => merged_packet_count_A_bus,
1420  merged_fifo_error_A_bus => merged_fifo_error_A_bus,
1421  TOB_packet_merged_A_bus => TOB_packet_merged_A_bus,
1422  TOB_packet_missing_A_bus => TOB_packet_missing_A_bus,
1423  debug_packet_created_A_bus => debug_packet_created_A_bus,
1424 -- TOB FIFO status block B
1425  tob_fifo_fill_level_B_bus => tob_fifo_fill_level_B_bus,
1426  tob_packet_count_B_bus => tob_packet_count_B_bus,
1427  tob_fifo_error_B_bus => tob_fifo_error_B_bus,
1428  merged_fifo_fill_level_B_bus => merged_fifo_fill_level_B_bus,
1429  merged_packet_count_B_bus => merged_packet_count_B_bus,
1430  merged_fifo_error_B_bus => merged_fifo_error_B_bus,
1431  TOB_packet_merged_B_bus => TOB_packet_merged_B_bus,
1432  TOB_packet_missing_B_bus => TOB_packet_missing_B_bus,
1433  debug_packet_created_B_bus => debug_packet_created_B_bus,
1434 -- MUX status
1435  mux_active_bus => mux_active_bus,
1436  mux_l1id_valid_bus => mux_l1id_valid_bus,
1437  mux_source_bus => mux_source_bus,
1438  mux_l1id_bus => mux_l1id_bus,
1439 -- Raw FIFO status block
1440  raw_fifo_fill_level_bus => raw_fifo_fill_level_bus,
1441  raw_packet_count_bus => raw_packet_count_bus,
1442  raw_fifo_error_bus => raw_fifo_error_bus,
1443 -- MGT flow control
1444  tob_mgt_xoff_bus => mgt_xoff_bus(3 downto 0),
1445  raw_mgt_xoff_bus => mgt_xoff_bus(7 downto 4),
1446 -- BUSY control
1447  tob_busy_bus => busy_bus(3 downto 0),
1448  raw_busy_bus => busy_bus(7 downto 4),
1449 -- Merging block flow control
1450  Block_A_pause => TOB_Block_A_pause,
1451  Block_B_pause => TOB_Block_B_pause
1452  );
1453 
1454 -- generate ECR and BCR in 320 MHz domain from initial TTC signals
1455 
1456 bcr_clk40 : process(clk40)
1457  begin
1458  if rising_edge(clk40) then
1459  if (bcr_40 = '1') then
1460  bcr_40_tff <= not bcr_40_tff;
1461  else
1462  bcr_40_tff <= bcr_40_tff;
1463  end if;
1464  end if;
1465  end process bcr_clk40;
1466 
1467 ecr_clk40 : process(clk40)
1468  begin
1469  if rising_edge(clk40) then
1470  if (ecr_40 = '1') then
1471  ecr_40_tff <= not ecr_40_tff;
1472  else
1473  ecr_40_tff <= ecr_40_tff;
1474  end if;
1475  end if;
1476  end process ecr_clk40;
1477 
1478 bcr_tff_clk320 : process(clk_320)
1479  begin
1480  if rising_edge(clk_320) then
1481  bcr_320_tff_buf <= bcr_320_tff_buf(0) & bcr_40_tff;
1482  end if;
1483  end process bcr_tff_clk320;
1484 
1485 ecr_tff_clk320 : process(clk_320)
1486  begin
1487  if rising_edge(clk_320) then
1488  ecr_320_tff_buf <= ecr_320_tff_buf(0) & ecr_40_tff;
1489  end if;
1490  end process ecr_tff_clk320;
1491 
1492 bcr_clk320 : process(clk_320)
1493  begin
1494  if rising_edge(clk_320) then
1495  if ((bcr_320_tff_buf(1) xor bcr_320_tff_buf(0)) = '1') then
1496  bcr_320 <= '1';
1497  else
1498  bcr_320 <= '0';
1499  end if;
1500  end if;
1501  end process bcr_clk320;
1502 
1503 ecr_clk320 : process(clk_320)
1504  begin
1505  if rising_edge(clk_320) then
1506  if ((ecr_320_tff_buf(1) xor ecr_320_tff_buf(0)) = '1') then
1507  ecr_320 <= '1';
1508  else
1509  ecr_320 <= '0';
1510  end if;
1511  end if;
1512  end process ecr_clk320;
1513 
1514 Reset_block: process(clk_320)
1515  Variable stretch: std_logic_vector(7 downto 0) := (Others => '1');
1516  Variable first_reset: std_logic := '0';
1517  begin
1518 -- Reset on ECR
1519  if rising_edge(clk_320) then
1520  if (first_reset = '0') or (rst_320 = '1') then
1521  stretch := (Others => '1');
1522  first_reset := '1';
1523  else
1524  stretch := stretch(6 downto 0) & "0";
1525  end if;
1526  if (rst_320_sig = '1') and (stretch(7) = '0') then
1527  rst_320_end <= '1'
1528 -- pragma translate_off
1529  after 2 ns
1530 -- pragma translate_on
1531  ;
1532  else
1533  rst_320_end <= '0'
1534 -- pragma translate_off
1535  after 2 ns
1536 -- pragma translate_on
1537  ;
1538  end if;
1539  rst_320_sig <= stretch(7)
1540 -- pragma translate_off
1541  after 2 ns
1542 -- pragma translate_on
1543  ;
1544  end if;
1545  end process Reset_block;
1546 
1547 SRLC32E_reset_delay : SRLC32E
1548 -- generate a delayed pulse after end of reset
1549  generic map (
1550  INIT => X"00000000")
1551  port map (
1552  Q => Open,
1553  Q31 => rst_320_delay, -- SRL cascaded data output
1554  A => (Others => '1'), -- Select input
1555  CE => '1', -- Clock enable input
1556  CLK => clk_320, -- Clock input
1557  D => rst_320_end -- SRL data input
1558  );
1559 
1560 L1A_enable_block: process(clk_320)
1561  begin
1562  if rising_edge(clk_320) then
1563  l1a_enable_sig <= l1a_enable
1564 -- pragma translate_off
1565  after 2 ns
1566 -- pragma translate_on
1567  ;
1568  end if;
1569  end process L1A_enable_block;
1570 
1571 Enable_block: process(clk_320)
1572  Variable source_enable_var, raw_destination_select_var : std_logic_vector(NProcessorFPGA*2 - 1 downto 0) := (Others => '0');
1573  Variable tob_destination_enable_var : std_logic_vector(1 downto 0) := (Others => '0');
1574  Variable mux_enable_A_var, mux_enable_B_var : std_logic_vector(5 downto 0); -- Raw(3 downto 0), Debug, TOB
1575  Variable mux_xon_A_mask, mux_xon_B_mask : std_logic_vector(5 downto 0); -- Raw(3 downto 0), Debug, TOB
1576  begin
1577  if rising_edge(clk_320) then
1578  if (rst_320_sig = '1') then
1579  source_enable_var := (Others => '0');
1580  tob_destination_enable_var := (Others => '0');
1581  raw_destination_select_var := (Others => '0');
1582  mux_enable_A_var := (Others => '0');
1583  mux_enable_B_var := (Others => '0');
1584  elsif (rst_320_delay = '1') then
1585  source_enable_var := source_enable;
1586  tob_destination_enable_var := tob_destination_enable;
1587  mux_enable_A_var(1 downto 0) := tob_destination_enable(0) & tob_destination_enable(0);
1588  mux_enable_B_var(1 downto 0) := tob_destination_enable(1) & tob_destination_enable(1);
1589  Case raw_destination_enable is
1590  When "11" =>
1591  raw_destination_select_var := "10100101";
1592  mux_enable_A_var(5 downto 2) := "0011";
1593  mux_enable_B_var(5 downto 2) := "1100";
1594  When "01" =>
1595  raw_destination_select_var := "01010101";
1596  mux_enable_A_var(5 downto 2) := "1111";
1597  mux_enable_B_var(5 downto 2) := "0000";
1598  When "10" =>
1599  raw_destination_select_var := "10101010";
1600  mux_enable_A_var(5 downto 2) := "0000";
1601  mux_enable_B_var(5 downto 2) := "1111";
1602  When Others =>
1603  raw_destination_select_var := (Others => '0');
1604  mux_enable_A_var(5 downto 2) := "0000";
1605  mux_enable_B_var(5 downto 2) := "0000";
1606  End case;
1607  end if;
1608  if tob_xoff_bus(0) = '0' then
1609  mux_xon_A_mask(0) := '1';
1610  else
1611  mux_xon_A_mask(0) := '0';
1612  end if;
1613  if tob_xoff_bus(1) = '0' then
1614  mux_xon_B_mask(0) := '1';
1615  else
1616  mux_xon_B_mask(0) := '0';
1617  end if;
1618  if raw_xoff_bus(0) = '0' then
1619  mux_xon_A_mask(5 downto 1) := "11111";
1620  else
1621  mux_xon_A_mask(5 downto 1) := "00000";
1622  end if;
1623  if raw_xoff_bus(1) = '0' then
1624  mux_xon_B_mask(5 downto 1) := "11111";
1625  else
1626  mux_xon_B_mask(5 downto 1) := "00000";
1627  end if;
1628  if (l1a_enable_sig = '1') then
1629  source_enable_sig <= source_enable_var
1630 -- pragma translate_off
1631  after 2 ns
1632 -- pragma translate_on
1633  ;
1634  tob_destination_enable_sig <= tob_destination_enable_var
1635 -- pragma translate_off
1636  after 2 ns
1637 -- pragma translate_on
1638  ;
1639  raw_destination_select_sig <= raw_destination_select_var
1640 -- pragma translate_off
1641  after 2 ns
1642 -- pragma translate_on
1643  ;
1644  mux_enable_A_bus <= mux_enable_A_var and mux_xon_A_mask
1645 -- pragma translate_off
1646  after 2 ns
1647 -- pragma translate_on
1648  ;
1649  mux_enable_B_bus <= mux_enable_B_var and mux_xon_B_mask
1650 -- pragma translate_off
1651  after 2 ns
1652 -- pragma translate_on
1653  ;
1654  else
1655  source_enable_sig <= (Others => '0')
1656 -- pragma translate_off
1657  after 2 ns
1658 -- pragma translate_on
1659  ;
1660  tob_destination_enable_sig <= (Others => '0')
1661 -- pragma translate_off
1662  after 2 ns
1663 -- pragma translate_on
1664  ;
1665  raw_destination_select_sig <= (Others => '0')
1666 -- pragma translate_off
1667  after 2 ns
1668 -- pragma translate_on
1669  ;
1670  mux_enable_A_bus <= (Others => '0')
1671 -- pragma translate_off
1672  after 2 ns
1673 -- pragma translate_on
1674  ;
1675  mux_enable_B_bus <= (Others => '0')
1676 -- pragma translate_off
1677  after 2 ns
1678 -- pragma translate_on
1679  ;
1680  end if;
1681  end if;
1682  end process Enable_block;
1683 
1684 END Architecture rtl;
efex_packet_builder
AXI-stream version of packet engine...
Definition: efex_packet_builder.vhd:13
efex_packet_builder.packet_data
in packet_data std_logic_vector( 63 DOWNTO 0)
FIFO signals.
Definition: efex_packet_builder.vhd:18
efex_packet_builder.payload_data
out payload_data std_logic_vector( 63 DOWNTO 0)
towards Aurora readout
Definition: efex_packet_builder.vhd:23
efex_packet_mux
AXI-stream MUX into packet engine...
Definition: efex_packet_mux.vhd:23
efex_packet_mux.packet_mux_data
in packet_mux_data packet_data_array( NSRC- 1 downto 0)
Input signals.
Definition: efex_packet_mux.vhd:35
efex_packet_mux.packet_data
out packet_data std_logic_vector( 63 DOWNTO 0)
FIFO signals.
Definition: efex_packet_mux.vhd:40
efex_tob_merger
Definition: efex_tob_merger.vhd:13
fifo_selector
Switch FIFO data to correct stream depending on destination_enable...
Definition: fifo_selector.vhd:16
fifo_spy
Capture FIFO traffic into IPBus DPRAM64...
Definition: fifo_spy.vhd:21
fwft_register
Definition: fwft_register.vhd:8
mgt_buffer
Second version of packet format engine from MGT through to formatted (sub)block...
Definition: mgt_buffer.vhd:19
packet_block.rtl
Instantiate the readout merging and routing logic...
Definition: packet_block.vhd:99
packet_block.rtl.efex_packet_builder
efex_packet_builder
FIFO signals.
Definition: packet_block.vhd:101
packet_block
Instantiate the readout merging and routing logic...
Definition: packet_block.vhd:43
packet_fifo_block
Instantiate a Block RAM storage and Distributed RAM AXI interface block...
Definition: packet_fifo_block.vhd:16
packet_fifo_reset_block
Assert reset on error in FIFO and hold until end of incoming packet...
Definition: packet_fifo_reset_block.vhd:13
packet_fifo
Optimised RAM-based single clock packet FIFO.
Definition: packet_fifo.vhd:14
packet_fifo.out_data
out out_data STD_LOGIC_VECTOR( DATA_WIDTH- 1 downto 0)
AXI stream output.
Definition: packet_fifo.vhd:37
packet_fifo.in_data
in in_data STD_LOGIC_VECTOR( DATA_WIDTH- 1 downto 0)
AXI stream input.
Definition: packet_fifo.vhd:27
packet_fifo.in_pause
out in_pause STD_LOGIC
AXI stream input pause request.
Definition: packet_fifo.vhd:33
packet_fifo.out_error
out out_error STD_LOGIC
AXI stream output error (asserted on last)
Definition: packet_fifo.vhd:44
packet_fifo.rst_clk
in rst_clk STD_LOGIC
Synchronous reset.
Definition: packet_fifo.vhd:25
packet_fifo.clk
in clk STD_LOGIC
Clock.
Definition: packet_fifo.vhd:23
packet_fifo.DATA_WIDTH
DATA_WIDTH positive := 64
Width of data for RAM.
Definition: packet_fifo.vhd:17
packet_fifo.out_valid
out out_valid STD_LOGIC
AXI stream output valid.
Definition: packet_fifo.vhd:39
packet_fifo.in_last
in in_last STD_LOGIC
AXI stream input last.
Definition: packet_fifo.vhd:31
packet_fifo.in_valid
in in_valid STD_LOGIC
AXI stream input valid.
Definition: packet_fifo.vhd:29
packet_fifo.out_ready
in out_ready STD_LOGIC
AXI stream output ready.
Definition: packet_fifo.vhd:35
packet_fifo.out_last
out out_last STD_LOGIC
AXI stream output last.
Definition: packet_fifo.vhd:41
packet_fifo.BUFWIDTH
BUFWIDTH positive := 4
Width of address bus for buffer, i.e. array (0 to 2**BUFWIDTH - 1)
Definition: packet_fifo.vhd:20
packet_mux_type
Definition: packet_mux_type.vhd:4
packet_ram_fifo
Optimised RAM-based single clock packet FIFO.
Definition: packet_ram_fifo.vhd:16
packet_ram_fifo.out_data
out out_data STD_LOGIC_VECTOR( DATA_WIDTH- 1 downto 0)
AXI stream output.
Definition: packet_ram_fifo.vhd:39
packet_ram_fifo.in_data
in in_data STD_LOGIC_VECTOR( DATA_WIDTH- 1 downto 0)
AXI stream input.
Definition: packet_ram_fifo.vhd:31
packet_ram_fifo.MAXWIDTH
MAXWIDTH positive := 5
Parameter for maximum packet size (2**MAXWIDTH - 1) on input or output before trigger reset mechanism...
Definition: packet_ram_fifo.vhd:24
packet_ram_fifo.out_error
out out_error STD_LOGIC
AXI stream output error (asserted on last)
Definition: packet_ram_fifo.vhd:52
packet_ram_fifo.rst_clk
in rst_clk STD_LOGIC
Synchronous reset.
Definition: packet_ram_fifo.vhd:29
packet_ram_fifo.packet_count
out packet_count STD_LOGIC_VECTOR( 15 downto 0)
Number of packets stored in the FIFO.
Definition: packet_ram_fifo.vhd:47
packet_ram_fifo.clk
in clk STD_LOGIC
Clock.
Definition: packet_ram_fifo.vhd:27
packet_ram_fifo.DATA_WIDTH
DATA_WIDTH positive := 64
Width of data for RAM.
Definition: packet_ram_fifo.vhd:19
packet_ram_fifo.out_pause
in out_pause STD_LOGIC
AXI stream output pause request.
Definition: packet_ram_fifo.vhd:37
packet_ram_fifo.out_valid
out out_valid STD_LOGIC
AXI stream output valid.
Definition: packet_ram_fifo.vhd:41
packet_ram_fifo.in_last
in in_last STD_LOGIC
AXI stream input last.
Definition: packet_ram_fifo.vhd:35
packet_ram_fifo.in_valid
in in_valid STD_LOGIC
AXI stream input valid.
Definition: packet_ram_fifo.vhd:33
packet_ram_fifo.fifo_fill_level
out fifo_fill_level STD_LOGIC_VECTOR( 15 downto 0)
Number of words stored in the FIFO.
Definition: packet_ram_fifo.vhd:45
packet_ram_fifo.BUFWIDTH
BUFWIDTH positive := 10
Width of address bus for RAM, i.e. array (0 to 2**BUFWIDTH - 1)
Definition: packet_ram_fifo.vhd:21
packet_ram_fifo.out_last
out out_last STD_LOGIC
AXI stream output last.
Definition: packet_ram_fifo.vhd:43
packet_ram_fifo.in_error
out in_error STD_LOGIC
AXI stream input error.
Definition: packet_ram_fifo.vhd:49
packet_status_block
Instantiate the readout merging and routing FIFO status and control interface to IPBus....
Definition: packet_status_block.vhd:56
packet_status_block.RAW_FIFO_ADDR_MAX_WIDTH
RAW_FIFO_ADDR_MAX_WIDTH positive := 11
address bus width of merged FIFO RAMs after TOB merging
Definition: packet_status_block.vhd:62
packet_status_block.MERGED_FIFO_ADDR_MAX_WIDTH
MERGED_FIFO_ADDR_MAX_WIDTH positive := 11
address bus width of TOB FIFO RAM in packet_fifo_block for each Processor FPGA
Definition: packet_status_block.vhd:60
packet_status_block.MAX_PACKET_WIDTH
MAX_PACKET_WIDTH positive := 8
address bus width of RAW FIFO RAM in packet_fifo_block for each Processor FPGA address bus width of m...
Definition: packet_status_block.vhd:66
tob_merger_spy
Definition: tob_merger_spy.vhd:15
ttc_fifo_block
Switch TTC FIFO data to correct stream depending on destination_enable...
Definition: ttc_fifo_block.vhd:15
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