tob_merger_spy.vhd

-- MUX TOB packets into spy RAM when error in input data or debug packet created...
--
-- Dave Sankey, November 2022
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
LIBRARY infrastructure_lib;
use infrastructure_lib.packet_mux_type.all;
 
LIBRARY ipbus_lib;
USE ipbus_lib.ipbus.all;
 
entity tob_merger_spy is
  GENERIC(
    RAM_ADDR_WIDTH  : positive := 10
  );
  port (
    clk_320             : in std_logic;
    rst_320             : in std_logic;
--  TOB MGT status signals
    tob_mgt_packet_err_bus  : in std_logic_vector(3 downto 0);
    tob_mgt_length_err_bus  : in std_logic_vector(3 downto 0);
    tob_mgt_last_l1id_bus   : in mgt_data_array(3 downto 0);
-- Merger status signals
    L1A_seen            : in std_logic;
    Last_L1ID_merged    : in std_logic_vector(31 downto 0); -- ECRID and L1ID
-- Merger output FIFO signals
    merged_fifo_data    : in packet_data_array(1 downto 0);
    merged_fifo_valid   : in std_logic_vector(1 downto 0);
    merged_fifo_last    : in std_logic_vector(1 downto 0);
-- interface to IPBus
    clk_ipb             : in std_logic;
    rst_ipb             : in std_logic;
    rst_ipbus_addr      : in std_logic;
    ipbus_wraparound    : in std_logic;
    ipb_in              : in ipb_wbus;
    ipb_out             : out ipb_rbus
  );
end entity tob_merger_spy;
 
Architecture rtl of tob_merger_spy is
 
Component fifo_spy IS
  GENERIC(
    IPBUS_ADDR_WIDTH    : positive := 10
  );
  port (
--- data to FIFO
    clk_320             : in std_logic;
    rst_320             : in std_logic;
    fifo_data           : in std_logic_vector (63 DOWNTO 0);
    fifo_valid          : in std_logic;
    fifo_last           : in std_logic;
    fifo_tready         : in std_logic;
-- interface to IPBus
    clk_ipb             : in std_logic;
    rst_ipb             : in std_logic;
    rst_ipbus_addr      : in std_logic;
    ipbus_wraparound    : in std_logic;
    ipb_in              : in ipb_wbus;
    ipb_out             : out ipb_rbus
  );
END Component fifo_spy;
 
signal bad_l1id_sig, send_tob_sig, spy_last_sig, spy_valid_sig: std_logic;
signal spy_data_sig: std_logic_vector (63 DOWNTO 0);
 
Begin
 
-- This logic only really works if the MGT errors are few and far between
-- so that there is only one error out there at any particular moment in time
-- between when it is latched in the MGT and subsequently caught in the merger.
-- Or more generally only the last error is guaranteed to be caught...
Bad_mgt_L1ID_latch: process(clk_320)
variable error_pending_bus: std_logic_vector(3 downto 0) := (Others => '0');
variable last_error_l1id_bus: mgt_data_array(3 downto 0) := (Others => (Others => '0'));
variable found_bad_l1id: std_logic := '0';
begin
    if (rising_edge(clk_320)) then
        if (rst_320 = '1') then
            error_pending_bus := (Others => '0');
            for i in 3 downto 0 loop
                last_error_l1id_bus(i) := (Others => '0');
            end loop;
        else
            found_bad_l1id := '0';
            for i in 3 downto 0 loop
                if (L1A_seen = '1') and (error_pending_bus(i) = '1') and (Last_L1ID_merged = last_error_l1id_bus(i)) then
                    error_pending_bus(i) := '0';
                    found_bad_l1id := '1';
                end if;
                if (tob_mgt_packet_err_bus(i) = '1') or (tob_mgt_length_err_bus(i) = '1') then
                    last_error_l1id_bus(i) := tob_mgt_last_l1id_bus(i);
                    error_pending_bus(i) := '1';
                end if;
            end loop;
        end if;
        bad_l1id_sig <= found_bad_l1id;
    end if;
end process Bad_mgt_L1ID_latch;
 
-- Send TOB packet to debug spy if we latched an error in the MGT processing or we send a packet to debug for this event
send_tob_latch: process(clk_320)
variable send_tob: std_logic := '0';
begin
    if (rising_edge(clk_320)) then
        if (rst_320 = '1') or (L1A_seen = '1') then
            send_tob := '0';
        elsif (bad_l1id_sig = '1') or (merged_fifo_valid(1) = '1') then
            send_tob := '1';
        end if;
        send_tob_sig <= send_tob;
    end if;
end process send_tob_latch;
 
send_to_spy_block: process(clk_320)
variable spy_data: std_logic_vector(63 downto 0);
variable spy_valid, spy_last: std_logic;
begin
    if (rising_edge(clk_320)) then
        if (merged_fifo_valid(1) = '1') then
            spy_data := merged_fifo_data(1);
            spy_last := merged_fifo_last(1);
            spy_valid := '1';
        elsif (merged_fifo_valid(0) = '1') and (send_tob_sig = '1') then
            spy_data := merged_fifo_data(0);
            spy_last := merged_fifo_last(0);
            spy_valid := '1';
        else
            spy_data := (Others => '0');
            spy_last := '0';
            spy_valid := '0';
        end if;
        spy_data_sig <= spy_data;
        spy_last_sig <= spy_last;
        spy_valid_sig <= spy_valid;
    end if;
end process send_to_spy_block;
 
debug_spy : fifo_spy
    GENERIC map (
        IPBUS_ADDR_WIDTH    => RAM_ADDR_WIDTH
    )
    port map (
--- data to FIFO
        clk_320             => clk_320,
        rst_320             => rst_320,
        fifo_data           => spy_data_sig,
        fifo_valid          => spy_valid_sig,
        fifo_last           => spy_last_sig,
        fifo_tready         => '1',
-- interface to IPBus for spy RAM
        clk_ipb             => clk_ipb,
        rst_ipb             => rst_ipb,
        rst_ipbus_addr      => rst_ipbus_addr,
        ipbus_wraparound    => ipbus_wraparound,
        ipb_in              => ipb_in,
        ipb_out             => ipb_out
    );
 
END Architecture rtl;