tob_merger_spy Entity Reference

Inheritance diagram for tob_merger_spy:

Entities
rtl	architecture

Libraries
ieee
infrastructure_lib
ipbus_lib

Use Clauses
std_logic_1164
numeric_std
packet_mux_type	Package <packet_mux_type>
ipbus

Generics
RAM_ADDR_WIDTH	positive := 10

Ports
clk_320	in	std_logic
rst_320	in	std_logic
tob_mgt_packet_err_bus	in	std_logic_vector ( 3 downto 0 )
tob_mgt_length_err_bus	in	std_logic_vector ( 3 downto 0 )
tob_mgt_last_l1id_bus	in	mgt_data_array ( 3 downto 0 )
L1A_seen	in	std_logic
Last_L1ID_merged	in	std_logic_vector ( 31 downto 0 )
merged_fifo_data	in	packet_data_array ( 1 downto 0 )
merged_fifo_valid	in	std_logic_vector ( 1 downto 0 )
merged_fifo_last	in	std_logic_vector ( 1 downto 0 )
clk_ipb	in	std_logic
rst_ipb	in	std_logic
rst_ipbus_addr	in	std_logic
ipbus_wraparound	in	std_logic
ipb_in	in	ipb_wbus
ipb_out	out	ipb_rbus

Detailed Description

Definition at line 15 of file tob_merger_spy.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/tob_merger_spy.vhd