packet_ram_fifo.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
 
entity packet_ram_fifo is
    Generic (
        DATA_WIDTH: positive := 64;
        constant BUFWIDTH: positive := 10;
        constant MAXWIDTH: positive := 5
    );
    Port (
        clk             : in  STD_LOGIC;
        rst_clk         : in  STD_LOGIC;
        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        in_valid        : in  STD_LOGIC;
        in_last         : in  STD_LOGIC;
        out_pause       : in  STD_LOGIC;
        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        out_valid       : out STD_LOGIC;
        out_last        : out STD_LOGIC;
        fifo_fill_level : out STD_LOGIC_VECTOR(15 downto 0);
        packet_count    : out STD_LOGIC_VECTOR(15 downto 0);
        in_error        : out STD_LOGIC;
        out_error       : out STD_LOGIC
    );
end packet_ram_fifo;
 
architecture Behavioral of packet_ram_fifo is
 
type FIFO_Memory is array (0 to 2**BUFWIDTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH downto 0);
signal Memory : FIFO_Memory;
attribute ram_style : string;
attribute ram_style of Memory : signal is "block";
 
signal fifo_fill_level_sig, write_ptr, read_ptr, new_read_ptr, read_addr, read_reg, npacket_sig : unsigned(BUFWIDTH-1 downto 0);
signal mem_out_reg, mem_out_data: STD_LOGIC_VECTOR(DATA_WIDTH downto 0);
signal in_data_reg: STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
signal rst_reg, in_valid_reg, in_last_reg, out_valid_sig, error_sig, input_error_sig, reset_ptr, running_sig, input_ok_sig: STD_LOGIC;
signal packet_change_sig: STD_LOGIC_VECTOR(1 downto 0);
 
begin
 
    out_data <= mem_out_data(DATA_WIDTH-1 downto 0)
-- pragma translate_off
    when out_valid_sig = '1' else (others => '0')
-- pragma translate_on
    ;
    out_last <= mem_out_data(DATA_WIDTH) or error_sig
-- pragma translate_off
    when out_valid_sig = '1' else '0'
-- pragma translate_on
    ;
    in_error <= input_error_sig;
    out_error <= error_sig;
    out_valid <= out_valid_sig;
    fifo_fill_level(BUFWIDTH-1 downto 0) <= STD_LOGIC_VECTOR(fifo_fill_level_sig);
    fifo_fill_level(15 downto BUFWIDTH) <= (Others => '0');
    packet_count(BUFWIDTH-1 downto 0) <= STD_LOGIC_VECTOR(npacket_sig);
    packet_count(15 downto BUFWIDTH) <= (Others => '0');
 
    input_reg: process (clk)
    begin
        if rising_edge(clk) then
            in_data_reg <= in_data
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            in_valid_reg <= in_valid
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            in_last_reg <= in_last
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            rst_reg <= rst_clk
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process input_reg;
 
    input_block: process (clk)
    begin
        if rising_edge(clk) then
            if (in_valid_reg = '1') and (input_ok_sig = '1') then
                -- Write Data to Memory
                Memory(to_integer(write_ptr)) <= (in_last_reg or input_error_sig) & in_data_reg
-- pragma translate_off
                after 2 ns
-- pragma translate_on
                ;
            end if;
        end if;
    end process input_block;
 
-- Check for excessive input blocks, veto rest of packet if overrun
    input_error_block: process (clk)
        variable Watchdog : unsigned(MAXWIDTH downto 0);
        variable input_error, input_ok : STD_LOGIC;
    begin
        if rising_edge(clk) then
            if rst_reg = '1' then
                Watchdog := (Others => '0');
                input_ok := '1';
                input_error := '0';
            else
-- if watchdog has fired veto rest of packet until tlast
                if (in_valid_reg = '1') and (in_last_reg = '1') then
                    input_ok := '1';
                elsif (input_error_sig = '1') then
                    input_ok := '0';
                end if;
                input_error := '0';
                if (in_valid = '1') then
                    if (in_last = '1') then
                        Watchdog := (Others => '0');
                    else
                        Watchdog := Watchdog + 1;
                    end if;
                    if (Watchdog(MAXWIDTH) = '1') and (input_ok = '1') then
                        input_error := '1';
                    end if;
                end if;
            end if;
            input_error_sig <= input_error
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            input_ok_sig <= input_ok
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process input_error_block;
 
    output_block: process (clk)
    begin
        if rising_edge(clk) then
            mem_out_reg <= Memory(to_integer(read_ptr))
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process output_block;
 
    output_reg: process (clk)
    begin
        if rising_edge(clk) then
            mem_out_data <= mem_out_reg
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process output_reg;
 
    -- Output Control Process
    fifo_proc : process (clk)
        variable Watchdog : unsigned(MAXWIDTH downto 0);
        variable error, packet_up, packet_down, Running : STD_LOGIC;
        variable packet_change: STD_LOGIC_VECTOR(1 downto 0);
        variable valid, reset_buf: std_logic_vector(2 downto 0);
    begin
        if rising_edge(clk) then
            packet_down := '0';
            packet_up := '0';
            if rst_reg = '1' then
                Watchdog := (Others => '0');
                Running := '0';
                reset_buf := (Others => '0');
                error := '1'; -- trigger (packet_change_sig = "11")...
            else
 
                if (in_valid_reg = '1') and (input_ok_sig = '1') then
                    if (in_last_reg = '1') or (input_error_sig = '1') then -- Last on incoming packet
                        packet_up := '1';
                    end if;
                end if;
 
                if (Running = '1') then
                    -- Stop running if out_last was sent
                    if ((error = '1') or (mem_out_data(DATA_WIDTH) = '1')) and (out_valid_sig = '1') then
                        Running := '0';
                        packet_down := '1';
                        reset_buf := (Others => '1');
                    elsif (out_valid_sig = '1') then
                        Watchdog := Watchdog + 1;
                    end if;
                elsif (npacket_sig /= 0) and (reset_buf(2) = '0') and (out_pause = '0') then
                    Running := '1';
                    Watchdog := (Others => '0');
                else
                    reset_buf := reset_buf(1 downto 0) & '0';
                end if;
 
            end if;
 
            If (Running = '1') then
                valid := valid(1 downto 0) & not out_pause;
                -- Die gracefully if the FIFO runs dry...
                If (fifo_fill_level_sig = 0) or (Watchdog(MAXWIDTH) = '1') then
                    error := '1';
                end if;
            else
                valid := (Others => '0');
            end if;
 
            if (Running = '0') and (error = '1') then
                packet_change := "11";
                error := '0';
            elsif (packet_up = packet_down) then
                packet_change := "00";
            else
                packet_change := packet_up & packet_down;
            end if;
 
            running_sig <= Running
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            error_sig <= error
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            reset_ptr <= reset_buf(0)
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            out_valid_sig <= valid(2)
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            packet_change_sig <= packet_change
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process fifo_proc;
 
    write_pointer_proc : process(clk)
        variable Head, NextHead : unsigned(BUFWIDTH downto 0);
    begin
        if rising_edge(clk) then
            if (packet_change_sig = "11") then
                NextHead := (Others => '0');
            else
                Head := "0" & write_ptr;
                if (in_valid_reg = '1') and (input_ok_sig = '1') then
                    NextHead := Head + 1;
                else
                    NextHead := Head;
                end if;
            end if;
            write_ptr <= NextHead(BUFWIDTH-1 downto 0)
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process write_pointer_proc;
 
    read_pointer_proc : process(clk)
        variable Tail, NextTail, ThisAddr, NextAddr : unsigned(BUFWIDTH downto 0);
    begin
        if rising_edge(clk) then
            if (packet_change_sig = "11") then
                NextTail := (Others => '0');
            else
                if (reset_ptr = '1') then
                    Tail := "0" & new_read_ptr;
                else
                    Tail := "0" & read_ptr;
                end if;
                if ((running_sig = '1') and (out_pause = '0')) then
                    NextTail := Tail + 1;
                else
                    NextTail := Tail;
                end if;
                ThisAddr := "0" & read_addr;
                NextAddr := ThisAddr + 1;
            end if;
            read_ptr <= NextTail(BUFWIDTH-1 downto 0)
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            read_reg <= read_ptr
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            read_addr <= read_reg
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            new_read_ptr <= NextAddr(BUFWIDTH-1 downto 0)
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process read_pointer_proc;
 
    packet_count_proc : process(clk)
        variable npacket : unsigned(BUFWIDTH-1 downto 0);
        constant zeros: unsigned(BUFWIDTH-1 downto 0) := (Others => '0');
    begin
        if rising_edge(clk) then
            Case packet_change_sig is
                When "11" =>
                    npacket := (Others => '0');
                When "10" =>
                    npacket := npacket + 1;
                When "01" =>
                    if (npacket /= zeros) then
                        npacket := npacket - 1;
                    end if;
                When Others =>
                    null;
            End Case;
            npacket_sig <= npacket
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process packet_count_proc;
 
    fill_level_proc : process(clk)
        variable FillLevel, Head, Tail : unsigned(BUFWIDTH downto 0);
    begin
        if rising_edge(clk) then
            if rst_reg = '1' then
                FillLevel := (Others => '0');
                Tail := (Others => '0');
            else
                Head := "1" & write_ptr;
                if (running_sig = '1') then
                    Tail := "0" & read_addr;
                elsif (reset_ptr = '1') then
                    Tail := "0" & new_read_ptr;
                end if;
                FillLevel := Head - Tail;
            end if;
            fifo_fill_level_sig <= FillLevel(BUFWIDTH-1 downto 0)
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process fill_level_proc;
 
end Behavioral;