Behavioral Architecture Reference

Optimised RAM-based single clock packet FIFO. More...

Processes
input_reg	( clk )
input_block	( clk )
input_error_block	( clk )
output_block	( clk )
output_reg	( clk )
fifo_proc	( clk )
write_pointer_proc	( clk )
read_pointer_proc	( clk )
packet_count_proc	( clk )
fill_level_proc	( clk )

Types
FIFO_Memory	( 0 to 2 ** BUFWIDTH - 1 ) STD_LOGIC_VECTOR ( DATA_WIDTH downto 0 )

Signals
Memory	FIFO_Memory
fifo_fill_level_sig	unsigned ( BUFWIDTH - 1 downto 0 )
write_ptr	unsigned ( BUFWIDTH - 1 downto 0 )
read_ptr	unsigned ( BUFWIDTH - 1 downto 0 )
new_read_ptr	unsigned ( BUFWIDTH - 1 downto 0 )
read_addr	unsigned ( BUFWIDTH - 1 downto 0 )
read_reg	unsigned ( BUFWIDTH - 1 downto 0 )
npacket_sig	unsigned ( BUFWIDTH - 1 downto 0 )
mem_out_reg	STD_LOGIC_VECTOR ( DATA_WIDTH downto 0 )
mem_out_data	STD_LOGIC_VECTOR ( DATA_WIDTH downto 0 )
in_data_reg	STD_LOGIC_VECTOR ( DATA_WIDTH - 1 downto 0 )
rst_reg	STD_LOGIC
in_valid_reg	STD_LOGIC
in_last_reg	STD_LOGIC
out_valid_sig	STD_LOGIC
error_sig	STD_LOGIC
input_error_sig	STD_LOGIC
reset_ptr	STD_LOGIC
running_sig	STD_LOGIC
input_ok_sig	STD_LOGIC
packet_change_sig	STD_LOGIC_VECTOR ( 1 downto 0 )

Attributes
ram_style	string
ram_style	signal is " block "

Detailed Description

Optimised RAM-based single clock packet FIFO.

AXI stream FIFO block that assumes in_ready is permanently asserted (flow control is defined elsewhere) and that flow control on out_pause is relaxed, so destination will always take data with out_valid asserted Originally derived from http://www.deathbylogic.com/2015/01/vhdl-first-word-fall-through-fifo/ Modified to drive AXI stream interface, with recovery for FIFO running empty or excessive packet size Waits until FIFO contains a complete packet before attempting to transmit

Author

David Sankey

Definition at line 56 of file packet_ram_fifo.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/packet_ram_fifo.vhd