packet_ram_fifo.vhd File Reference

Optimised RAM-based single clock packet FIFO. More...

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Entities
packet_ram_fifo	entity
	Optimised RAM-based single clock packet FIFO. More...
Behavioral	architecture
	Optimised RAM-based single clock packet FIFO. More...

Detailed Description

Optimised RAM-based single clock packet FIFO.

AXI stream FIFO block that assumes in_ready is permanently asserted (flow control is defined elsewhere) and that flow control on out_pause is relaxed, so destination will always take data with out_valid asserted Originally derived from http://www.deathbylogic.com/2015/01/vhdl-first-word-fall-through-fifo/ Modified to drive AXI stream interface, with recovery for FIFO running empty or excessive packet size Waits until FIFO contains a complete packet before attempting to transmit

Author

David Sankey

Definition in file packet_ram_fifo.vhd.