packet_fifo_block.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
ENTITY packet_fifo_block IS
  GENERIC(
    RAM_ADDR_WIDTH      : positive := 12;
    MAX_PACKET_WIDTH    : positive := 8
  );
  port (
    clk_320             : in std_logic;
    rst_320             : in std_logic;
--
    fifo_data           : in std_logic_vector (63 DOWNTO 0);
    fifo_valid          : in std_logic;
    fifo_last           : in std_logic;
--
    packet_data         : OUT std_logic_vector (63 DOWNTO 0);
    packet_valid        : OUT std_logic;
    packet_last         : OUT std_logic;
    packet_ready        : IN std_logic;
--
    fifo_fill_level     : out std_logic_vector(15 downto 0);
    packet_count        : out STD_LOGIC_VECTOR(15 downto 0);
    fifo_empty          : OUT std_logic;
    input_error         : OUT std_logic;
    fifo_error          : OUT std_logic
  );
END ENTITY packet_fifo_block;
 
Architecture rtl of packet_fifo_block is
 
Component packet_ram_fifo is
    Generic (
        DATA_WIDTH: positive := 64;
        constant BUFWIDTH: positive := 10;
        constant MAXWIDTH: positive := 5
    );
    Port (
        clk             : in  STD_LOGIC;
        rst_clk         : in  STD_LOGIC;
        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        in_valid        : in  STD_LOGIC;
        in_last         : in  STD_LOGIC;
        out_pause       : in  STD_LOGIC;
        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        out_valid       : out STD_LOGIC;
        out_last        : out STD_LOGIC;
        fifo_fill_level : out STD_LOGIC_VECTOR(15 downto 0);
        packet_count    : out STD_LOGIC_VECTOR(15 downto 0);
        in_error        : out STD_LOGIC;
        out_error       : out STD_LOGIC
    );
end Component packet_ram_fifo;
 
Component packet_fifo is
    Generic (
        DATA_WIDTH: positive := 64;
        constant BUFWIDTH: positive := 4
    );
    Port (
        clk             : in  STD_LOGIC;
        rst_clk         : in  STD_LOGIC;
        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        in_valid        : in  STD_LOGIC;
        in_last         : in  STD_LOGIC;
        in_pause        : out STD_LOGIC;
        out_ready       : in  STD_LOGIC;
        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        out_valid       : out STD_LOGIC;
        out_last        : out STD_LOGIC;
        out_error       : out STD_LOGIC
    );
end Component packet_fifo;
 
SIGNAL data_fifo_data : STD_LOGIC_VECTOR(63 DOWNTO 0);
signal fifo_fill_level_i : std_logic_vector(15 downto 0);
SIGNAL data_fifo_pause, data_fifo_valid, data_fifo_last, data_fifo_error, ram_fifo_error, local_reset : STD_LOGIC;
 
Begin
 
    data_ram_fifo : packet_ram_fifo
      Generic map (
        DATA_WIDTH => 64,
        BUFWIDTH => RAM_ADDR_WIDTH,
        MAXWIDTH => MAX_PACKET_WIDTH
      )
      Port map (
        clk             => clk_320,
        rst_clk         => local_reset,
        in_data         => fifo_data,
        in_valid        => fifo_valid,
        in_last         => fifo_last,
        out_pause       => data_fifo_pause,
        out_data        => data_fifo_data,
        out_valid       => data_fifo_valid,
        out_last        => data_fifo_last,
        fifo_fill_level => fifo_fill_level_i,
        packet_count    => packet_count,
        in_error        => input_error,
        out_error       => ram_fifo_error
      );
 
    data_fifo : packet_fifo
      Generic map (
        DATA_WIDTH => 64,
        BUFWIDTH => 4
      )
      Port map (
        clk             => clk_320,
        rst_clk         => local_reset,
        in_data         => data_fifo_data,
        in_valid        => data_fifo_valid,
        in_last         => data_fifo_last,
        in_pause        => data_fifo_pause,
        out_ready       => packet_ready,
        out_data        => packet_data,
        out_valid       => packet_valid,
        out_last        => packet_last,
        out_error       => data_fifo_error
      );
 
local_reset_block: process(clk_320)
    Variable stretch: std_logic_vector(7 downto 0) := (Others => '1');
    begin
-- Reset on incoming rst_320 or error out of either FIFO
        if rising_edge(clk_320) then
            if (ram_fifo_error = '1') or (data_fifo_error = '1') or (rst_320 = '1') then
                stretch := (Others => '1');
            else
                stretch := stretch(6 downto 0) & "0";
            end if;
            local_reset <= stretch(7)
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process local_reset_block;
 
fifo_empty_block: process(clk_320)
    begin
        if rising_edge(clk_320) then
            if (unsigned(fifo_fill_level_i) = 0) then
                fifo_empty <= '1'
-- pragma translate_off
                after 2 ns
-- pragma translate_on
                ;
            else
                fifo_empty <= '0'
-- pragma translate_off
                after 2 ns
-- pragma translate_on
                ;
            end if;
        end if;
    end process fifo_empty_block;
 
fifo_error <= ram_fifo_error or data_fifo_error;
fifo_fill_level <= fifo_fill_level_i;
 
END Architecture rtl;