packet_fifo_block Entity Reference

Instantiate a Block RAM storage and Distributed RAM AXI interface block... More...

Inheritance diagram for packet_fifo_block:

Entities
rtl	architecture
	Instantiate a Block RAM storage and Distributed RAM AXI interface block... More...

Libraries
ieee
	Use standard library.

Use Clauses
std_logic_1164
numeric_std

Generics
RAM_ADDR_WIDTH	positive := 12
MAX_PACKET_WIDTH	positive := 8

Ports
clk_320	in	std_logic
rst_320	in	std_logic
fifo_data	in	std_logic_vector ( 63 DOWNTO 0 )
fifo_valid	in	std_logic
fifo_last	in	std_logic
packet_data	out	std_logic_vector ( 63 DOWNTO 0 )
packet_valid	out	std_logic
packet_last	out	std_logic
packet_ready	in	std_logic
fifo_fill_level	out	std_logic_vector ( 15 downto 0 )
packet_count	out	STD_LOGIC_VECTOR ( 15 downto 0 )
fifo_empty	out	std_logic
input_error	out	std_logic
fifo_error	out	std_logic

Detailed Description

Instantiate a Block RAM storage and Distributed RAM AXI interface block...

Input to Block RAM always taken with flow control governed externally based on fifo_fill_level and packet_count ports fifo_error port is state of Distributed RAM and should never be asserted Output signals respect AXI stream flow control with FWFT

Author

David Sankey

Definition at line 16 of file packet_fifo_block.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd