rtl Architecture Reference

Instantiate a Block RAM storage and Distributed RAM AXI interface block... More...

Processes
local_reset_block	( clk_320 )
fifo_empty_block	( clk_320 )

Components
packet_ram_fifo	<Entity packet_ram_fifo>
packet_fifo	<Entity packet_fifo>

Signals
data_fifo_data	STD_LOGIC_VECTOR ( 63 DOWNTO 0 )
fifo_fill_level_i	std_logic_vector ( 15 downto 0 )
data_fifo_pause	STD_LOGIC
data_fifo_valid	STD_LOGIC
data_fifo_last	STD_LOGIC
data_fifo_error	STD_LOGIC
ram_fifo_error	STD_LOGIC
local_reset	STD_LOGIC

Instantiations
data_ram_fifo	packet_ram_fifo <Entity packet_ram_fifo>
data_fifo	packet_fifo <Entity packet_fifo>

Detailed Description

Instantiate a Block RAM storage and Distributed RAM AXI interface block...

Input to Block RAM always taken with flow control governed externally based on fifo_fill_level and packet_count ports fifo_error port is state of Distributed RAM and should never be asserted Output signals respect AXI stream flow control with FWFT

Author

David Sankey

Definition at line 43 of file packet_fifo_block.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/packet_fifo_block.vhd