packet_fifo Entity Reference

Optimised RAM-based single clock packet FIFO. More...

Inheritance diagram for packet_fifo:

Entities
Behavioral	architecture
	Optimised RAM-based single clock packet FIFO. More...

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
NUMERIC_STD

Generics
DATA_WIDTH	positive := 64
	Width of data for RAM.
BUFWIDTH	positive := 4
	Width of address bus for buffer, i.e. array (0 to 2**BUFWIDTH - 1)

Ports
clk	in	STD_LOGIC
		Clock.
rst_clk	in	STD_LOGIC
		Synchronous reset.
in_data	in	STD_LOGIC_VECTOR ( DATA_WIDTH - 1 downto 0 )
		AXI stream input.
in_valid	in	STD_LOGIC
		AXI stream input valid.
in_last	in	STD_LOGIC
		AXI stream input last.
in_pause	out	STD_LOGIC
		AXI stream input pause request.
out_ready	in	STD_LOGIC
		AXI stream output ready.
out_data	out	STD_LOGIC_VECTOR ( DATA_WIDTH - 1 downto 0 )
		AXI stream output.
out_valid	out	STD_LOGIC
		AXI stream output valid.
out_last	out	STD_LOGIC
		AXI stream output last.
out_error	out	STD_LOGIC
		AXI stream output error (asserted on last)

Detailed Description

Optimised RAM-based single clock packet FIFO.

AXI stream FIFO block that assumes in_ready is permanently asserted (flow control is defined elsewhere) Originally derived from http://www.deathbylogic.com/2015/01/vhdl-first-word-fall-through-fifo/ Modified to drive AXI stream interface, with recovery for FIFO running empty or excessive packet size

Author

David Sankey

Definition at line 14 of file packet_fifo.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/packet_fifo.vhd