Behavioral Architecture Reference

Optimised RAM-based single clock packet FIFO. More...

Processes
fifo_proc	( clk )
packet_count_proc	( clk )
fill_level_proc	( clk )

Signals
write_ptr	unsigned ( BUFWIDTH - 1 downto 0 )
read_ptr	unsigned ( BUFWIDTH - 1 downto 0 )
fifo_filled_sig	STD_LOGIC
fifo_empty_sig	STD_LOGIC
running_sig	STD_LOGIC
packet_ready_sig	STD_LOGIC
packet_change_sig	STD_LOGIC_VECTOR ( 1 downto 0 )

Detailed Description

Optimised RAM-based single clock packet FIFO.

AXI stream FIFO block that assumes in_ready is permanently asserted (flow control is defined elsewhere) Originally derived from http://www.deathbylogic.com/2015/01/vhdl-first-word-fall-through-fifo/ Modified to drive AXI stream interface, with recovery for FIFO running empty or excessive packet size

Author

David Sankey

Definition at line 48 of file packet_fifo.vhd.

---

The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/packet_fifo.vhd