packet_fifo.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
 
entity packet_fifo is
    Generic (
        DATA_WIDTH: positive := 64;
        constant BUFWIDTH: positive := 4
    );
    Port (
        clk             : in  STD_LOGIC;
        rst_clk         : in  STD_LOGIC;
        in_data         : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        in_valid        : in  STD_LOGIC;
        in_last         : in  STD_LOGIC;
        in_pause        : out STD_LOGIC;
        out_ready       : in  STD_LOGIC;
        out_data        : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        out_valid       : out STD_LOGIC;
        out_last        : out STD_LOGIC;
        out_error       : out STD_LOGIC
    );
end packet_fifo;
 
architecture Behavioral of packet_fifo is
signal write_ptr, read_ptr: unsigned(BUFWIDTH-1 downto 0);
signal fifo_filled_sig, fifo_empty_sig, running_sig, packet_ready_sig: STD_LOGIC;
signal packet_change_sig: STD_LOGIC_VECTOR(1 downto 0);
begin
 
    in_pause <= fifo_filled_sig;
    out_valid <= running_sig;
 
    -- Memory Pointer Process
    fifo_proc : process (clk)
        type FIFO_Memory is array(0 to 2**BUFWIDTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH downto 0);
        variable Memory : FIFO_Memory;
        variable DataOut: STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        variable last, packet_up, packet_down, error : STD_LOGIC;
        variable Head, Tail : natural range 0 to 2**BUFWIDTH - 1;
        variable Watchdog : unsigned(BUFWIDTH downto 0);
        variable Fatal, Running : STD_LOGIC;
        variable packet_change: STD_LOGIC_VECTOR(1 downto 0);
    begin
        if rising_edge(clk) then
            packet_down := '0';
            packet_up := '0';
            if rst_clk = '1' then
                Head := 0;
                Tail := 0;
                Watchdog := (Others => '0');
                Running := '0';
                Fatal := '0';
            else
                if ((out_ready = '1') and (Running = '1')) then
                    -- Update Tail pointer as needed
                    if (Tail = 2**BUFWIDTH - 1) then
                        Tail := 0;
                    else
                        Tail := Tail + 1;
                    end if;
 
                    -- And stop running if out_last was sent
                    if (last = '1') then
                        Running := '0';
                        packet_down := '1';
                        if Fatal = '1' then
                            Tail := Head;
                            Fatal := '0';
                        end if;
                    end if;
                    Watchdog := Watchdog + 1;
                end if;
 
                if (in_valid = '1') then
                    -- Write Data to Memory
                    Memory(Head) := in_last & in_data;
                    if (in_last = '1') then
                        packet_up := '1';
                    end if;
 
                    -- Increment Head pointer as needed
                    if (Head = 2**BUFWIDTH - 1) then
                        Head := 0;
                    else
                        Head := Head + 1;
                    end if;
                    Watchdog := (Others => '0');
                end if;
 
            end if;
 
            -- Start running when FIFO is half full or contains a full packet
            if (fifo_filled_sig = '1') or (packet_ready_sig = '1') then
                Running := '1';
            end if;
 
            If Running = '1' then
                -- Die gracefully if the FIFO runs dry...
                If (fifo_empty_sig = '1') or (Watchdog(BUFWIDTH) = '1') then
                    Fatal := '1';
                end if;
                If Fatal = '1' then
                    DataOut := (Others => '0');
                    last := '1';
                    error := '1';
                else
                -- Update data to be output
                    DataOut := Memory(Tail)(DATA_WIDTH-1 downto 0);
                    last := Memory(Tail)(DATA_WIDTH);
                    error := '0';
                end if;
            else
                DataOut := (Others => '0');
                last := '0';
                error := '0';
            end if;
            
            if (Fatal = '1') then
                packet_change := "11";
            elsif (packet_up = packet_down) then
                packet_change := "00";
            else
                packet_change := packet_up & packet_down;
            end if;
 
            write_ptr <= to_unsigned(Head, BUFWIDTH)
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            read_ptr <= to_unsigned(Tail, BUFWIDTH)
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            running_sig <= Running
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            out_data <= DataOut
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            out_error <= error
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            out_last <= last
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            packet_change_sig <= packet_change
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
 
        end if;
    end process fifo_proc;
 
    packet_count_proc : process(clk)
        variable npacket: unsigned(BUFWIDTH-1 downto 0);
        constant zeros: unsigned(BUFWIDTH-1 downto 0) := (Others => '0');
        variable packet_ready: std_logic;
    begin
        if rising_edge(clk) then
            if (rst_clk = '1') then
                npacket := (Others => '0');
            else
                Case packet_change_sig is
                    When "11" =>
                        npacket := (Others => '0');
                    When "10" =>
                        npacket := npacket + 1;
                    When "01" =>
                        if (npacket /= zeros) then
                            npacket := npacket - 1;
                        end if;
                    When Others =>
                        null;
                End Case;
            end if;
            if (npacket /= zeros) and (running_sig = '0') then
                packet_ready := '1';
            else
                packet_ready := '0';
            end if;
            packet_ready_sig <= packet_ready
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process packet_count_proc;
 
    fill_level_proc : process(clk)
        variable FillLevel, Head, Tail: unsigned(BUFWIDTH downto 0);
        variable Empty: std_logic;
    begin
        if rising_edge(clk) then
            if rst_clk = '1' then
                FillLevel := (Others => '0');
                Empty := '0';
            else
                if (write_ptr = read_ptr) then
                    Empty := '1';
                else
                    Empty := '0';
                end if;
                Head := "1" & write_ptr;
                Tail := "0" & read_ptr;
                FillLevel := Head - Tail;
            end if;
            fifo_filled_sig <= FillLevel(BUFWIDTH-1)
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
            fifo_empty_sig <= Empty
-- pragma translate_off
            after 2 ns
-- pragma translate_on
            ;
        end if;
    end process fill_level_proc;
 
end Behavioral;