packet_fifo_block.vhd File Reference

Instantiate a Block RAM storage and Distributed RAM AXI interface block... More...

Go to the source code of this file.

Entities
packet_fifo_block	entity
	Instantiate a Block RAM storage and Distributed RAM AXI interface block... More...
rtl	architecture
	Instantiate a Block RAM storage and Distributed RAM AXI interface block... More...

Detailed Description

Instantiate a Block RAM storage and Distributed RAM AXI interface block...

Input to Block RAM always taken with flow control governed externally based on fifo_fill_level and packet_count ports fifo_error port is state of Distributed RAM and should never be asserted Output signals respect AXI stream flow control with FWFT

Author

David Sankey

Definition in file packet_fifo_block.vhd.