packet_status_block Entity Reference

Instantiate the readout merging and routing FIFO status and control interface to IPBus... More...

Inheritance diagram for packet_status_block:

Entities
Behavioral	architecture

Libraries
ieee
	Use standard library.
ipbus_lib
infrastructure_lib

Use Clauses
std_logic_1164
numeric_std
ipbus
packet_mux_type	Package <packet_mux_type>

Generics
TOB_FIFO_ADDR_MAX_WIDTH	positive := 12
MERGED_FIFO_ADDR_MAX_WIDTH	positive := 11
	address bus width of TOB FIFO RAM in packet_fifo_block for each Processor FPGA
RAW_FIFO_ADDR_MAX_WIDTH	positive := 11
	address bus width of merged FIFO RAMs after TOB merging
MAX_PACKET_WIDTH	positive := 8
	address bus width of RAW FIFO RAM in packet_fifo_block for each Processor FPGA address bus width of maximum input packet (i.e. 8 implies 256 64 bit words), merged packets can be 4 times larger

Ports
clk_320	in	std_logic
rst_320	in	std_logic
clk_ipb	in	std_logic
rst_ipb	in	std_logic
bcr_320	in	std_logic
ecr_320	in	std_logic
ipb_in	in	ipb_wbus
ipb_out	out	ipb_rbus
ipbus_tob_mgt_wbus_array	out	ipb_wbus_array ( 3 downto 0 )
ipbus_tob_mgt_rbus_array	in	ipb_rbus_array ( 3 downto 0 )
ipbus_raw_mgt_wbus_array	out	ipb_wbus_array ( 3 downto 0 )
ipbus_raw_mgt_rbus_array	in	ipb_rbus_array ( 3 downto 0 )
ipbus_merger_spy_wbus_array	out	ipb_wbus_array ( 1 downto 0 )
ipbus_merger_spy_rbus_array	in	ipb_rbus_array ( 1 downto 0 )
ipbus_built_fifo_wbus_array	out	ipb_wbus_array ( 1 downto 0 )
ipbus_built_fifo_rbus_array	in	ipb_rbus_array ( 1 downto 0 )
rst_ipbus_tob_mgt_addr_bus	out	std_logic_vector ( 3 downto 0 )
ipbus_tob_mgt_wraparound_bus	out	std_logic_vector ( 3 downto 0 )
rst_ipbus_raw_mgt_addr_bus	out	std_logic_vector ( 3 downto 0 )
ipbus_raw_mgt_wraparound_bus	out	std_logic_vector ( 3 downto 0 )
rst_ipbus_merger_spy_addr_bus	out	std_logic_vector ( 1 downto 0 )
ipbus_merger_spy_wraparound_bus	out	std_logic_vector ( 1 downto 0 )
rst_ipbus_built_fifo_addr_bus	out	std_logic_vector ( 1 downto 0 )
ipbus_built_fifo_wraparound_bus	out	std_logic_vector ( 1 downto 0 )
readout_delay	out	std_logic_vector ( 31 downto 0 )
tob_mgt_packet_received_bus	in	std_logic_vector ( 3 downto 0 )
tob_mgt_safe_mode_bus	in	std_logic_vector ( 3 downto 0 )
tob_mgt_packet_err_bus	in	std_logic_vector ( 3 downto 0 )
tob_mgt_length_err_bus	in	std_logic_vector ( 3 downto 0 )
tob_mgt_bcn_err_bus	in	std_logic_vector ( 3 downto 0 )
tob_mgt_last_l1id_bus	in	mgt_data_array ( 3 downto 0 )
raw_mgt_packet_received_bus	in	std_logic_vector ( 3 downto 0 )
raw_mgt_safe_mode_bus	in	std_logic_vector ( 3 downto 0 )
raw_mgt_packet_err_bus	in	std_logic_vector ( 3 downto 0 )
raw_mgt_length_err_bus	in	std_logic_vector ( 3 downto 0 )
raw_mgt_last_l1id_bus	in	mgt_data_array ( 3 downto 0 )
tob_fifo_fill_level_A_bus	in	fifo_status_array ( 3 downto 0 )
tob_packet_count_A_bus	in	fifo_status_array ( 3 downto 0 )
tob_fifo_error_A_bus	in	std_logic_vector ( 3 downto 0 )
tob_fifo_fill_level_B_bus	in	fifo_status_array ( 3 downto 0 )
tob_packet_count_B_bus	in	fifo_status_array ( 3 downto 0 )
tob_fifo_error_B_bus	in	std_logic_vector ( 3 downto 0 )
Last_L1ID_merger_A	in	std_logic_vector ( 31 downto 0 )
Last_L1ID_merger_B	in	std_logic_vector ( 31 downto 0 )
L1A_seen_bus	in	std_logic_vector ( 1 downto 0 )
TOB_packet_merged_A_bus	in	std_logic_vector ( 3 downto 0 )
TOB_packet_missing_A_bus	in	std_logic_vector ( 3 downto 0 )
debug_packet_created_A_bus	in	std_logic_vector ( 3 downto 0 )
TOB_packet_merged_B_bus	in	std_logic_vector ( 3 downto 0 )
TOB_packet_missing_B_bus	in	std_logic_vector ( 3 downto 0 )
debug_packet_created_B_bus	in	std_logic_vector ( 3 downto 0 )
mux_active_bus	in	std_logic_vector ( 1 downto 0 )
mux_l1id_valid_bus	in	std_logic_vector ( 1 downto 0 )
mux_source_bus	in	std_logic_vector ( 7 downto 0 )
mux_l1id_bus	in	mgt_data_array ( 1 downto 0 )
merged_fifo_fill_level_A_bus	in	fifo_status_array ( 1 downto 0 )
merged_packet_count_A_bus	in	fifo_status_array ( 1 downto 0 )
merged_fifo_error_A_bus	in	std_logic_vector ( 1 downto 0 )
merged_fifo_fill_level_B_bus	in	fifo_status_array ( 1 downto 0 )
merged_packet_count_B_bus	in	fifo_status_array ( 1 downto 0 )
merged_fifo_error_B_bus	in	std_logic_vector ( 1 downto 0 )
raw_fifo_fill_level_bus	in	fifo_status_array ( 3 downto 0 )
raw_packet_count_bus	in	fifo_status_array ( 3 downto 0 )
raw_fifo_error_bus	in	std_logic_vector ( 3 downto 0 )
tob_mgt_xoff_bus	out	std_logic_vector ( 3 downto 0 )
raw_mgt_xoff_bus	out	std_logic_vector ( 3 downto 0 )
tob_busy_bus	out	std_logic_vector ( 3 downto 0 )
raw_busy_bus	out	std_logic_vector ( 3 downto 0 )
Block_A_pause	out	std_logic_vector ( 1 downto 0 )
Block_B_pause	out	std_logic_vector ( 1 downto 0 )

Detailed Description

Instantiate the readout merging and routing FIFO status and control interface to IPBus...

Instantiate the readout merging and routing FIFO status and control interface to IPBus

Performs the following functions:

i) Instantiate the IPBus fabric for the various registers and the spy RAMs

There are 8 input spy RAMs, one behind each incoming MGT and similarly 2 separate output spy RAMs into the 2 Aurora links.

ii) Instantiate the control registers for the various spy RAMs

There is a bit to reset the write address pointer and a bit to control wraparound in the RAM.

iii) Instantiate the monitoring registers for the various buffering FIFOs

There are two instances of the packet merging logic (one for each Aurora link). Each of these has 4 main buffering FIFOs for the TOB data (1 for each Processing FPGA), then 2 FIFOs after the merging logic (one for the merged TOB packet, one for any debug packets).

There are also 4 buffering FIFOs for the raw packets.

Each FIFO reports its occupancy and the number of packets it contains along with an overrun status every tick.

iv) Instantiate the flow control and associated monitoring for the various buffering FIFOs

For the FIFOs after the MGT there are XOFF bits towards each Processor FPGA for its TOB link and raw link.

This should be asserted if either of the two TOB FIFOs for TOB link bit or the raw FIFO for the raw link bit is over the XOFF assert threshold and cleared if the FIFOs are below the XOFF clear threshold.

For the FIFOs after the MGT there are also BUSY bits corresponding to each Processor FPGA TOB link and raw link.

This should be asserted if either of the two TOB FIFOs for TOB link or the raw FIFO for the raw link is over the BUSY assert threshold and cleared if the FIFOs are below the BUSY clear threshold.

For the FIFOs after the merging logic there is a pause bit for each instance of the packet merging logic.

This should be asserted if either the merged TOB FIFO or the debug FIFO is over the pause assert threshold and cleared if both FIFOs are below the pause clear threshold.

Author

Saeed Taghavi

Definition at line 56 of file packet_status_block.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/packet_status_block.vhd