Behavioral Architecture Reference

Processes
L1ID_latch	( clk_320 )
MUX_source_block	( clk_320 )
mux_a_bus_block	( clk_320 )
mux_b_bus_block	( clk_320 )
MUX_orbit_block	( clk_320 )

Signals
counter_control_i	std_logic_vector ( 31 downto 0 )
spy_ram_rst_wr_addr_i	std_logic_vector ( 31 downto 0 )
wraparound_enable_i	std_logic_vector ( 31 downto 0 )
rst_err_cntrs_i	std_logic
rst_status_cntrs_i	std_logic
rst_xoff_cntr_i	std_logic
tob_fifo_err_cnt_A_bus_i	mgt_data_array ( 3 downto 0 )
tob_fifo_err_cnt_B_bus_i	mgt_data_array ( 3 downto 0 )
raw_fifo_err_cnt_i	mgt_data_array ( 3 downto 0 )
merged_fifo_err_cnt_A_bus_i	mgt_data_array ( 1 downto 0 )
merged_fifo_err_cnt_B_bus_i	mgt_data_array ( 1 downto 0 )
tob_fifo_prog_full_thresh_assert_i	std_logic_vector ( 15 downto 0 )
tob_fifo_prog_full_thresh_negate_i	std_logic_vector ( 15 downto 0 )
raw_fifo_prog_full_thresh_assert_i	std_logic_vector ( 15 downto 0 )
raw_fifo_prog_full_thresh_negate_i	std_logic_vector ( 15 downto 0 )
tob_fifo_xoff_thresh_assert_i	std_logic_vector ( 15 downto 0 )
tob_fifo_xoff_thresh_negate_i	std_logic_vector ( 15 downto 0 )
merged_fifo_xoff_thresh_assert_i	std_logic_vector ( 15 downto 0 )
merged_fifo_xoff_thresh_negate_i	std_logic_vector ( 15 downto 0 )
raw_fifo_xoff_thresh_assert_i	std_logic_vector ( 15 downto 0 )
raw_fifo_xoff_thresh_negate_i	std_logic_vector ( 15 downto 0 )
dbg_fifo_xoff_thresh_assert_i	std_logic_vector ( 15 downto 0 )
dbg_fifo_xoff_thresh_negate_i	std_logic_vector ( 15 downto 0 )
fifo_bc_count_i	std_logic_vector ( 31 downto 0 )
tob_busy_cnt_32b_A_i	mgt_data_array ( 3 downto 0 )
tob_busy_active_cnt_32b_A_i	mgt_data_array ( 3 downto 0 )
tob_busy_assert_cnt_32b_A_i	mgt_data_array ( 3 downto 0 )
tob_busy_cnt_32b_B_i	mgt_data_array ( 3 downto 0 )
tob_busy_active_cnt_32b_B_i	mgt_data_array ( 3 downto 0 )
tob_busy_assert_cnt_32b_B_i	mgt_data_array ( 3 downto 0 )
tob_xoff_cnt_32b_A_i	mgt_data_array ( 3 downto 0 )
tob_xoff_active_cnt_32b_A_i	mgt_data_array ( 3 downto 0 )
tob_xoff_assert_cnt_32b_A_i	mgt_data_array ( 3 downto 0 )
tob_xoff_cnt_32b_B_i	mgt_data_array ( 3 downto 0 )
tob_xoff_active_cnt_32b_B_i	mgt_data_array ( 3 downto 0 )
tob_xoff_assert_cnt_32b_B_i	mgt_data_array ( 3 downto 0 )
raw_busy_cnt_32b_i	mgt_data_array ( 3 downto 0 )
raw_busy_active_cnt_32b_i	mgt_data_array ( 3 downto 0 )
raw_busy_assert_cnt_32b_i	mgt_data_array ( 3 downto 0 )
raw_xoff_cnt_32b_i	mgt_data_array ( 3 downto 0 )
raw_xoff_active_cnt_32b_i	mgt_data_array ( 3 downto 0 )
raw_xoff_assert_cnt_32b_i	mgt_data_array ( 3 downto 0 )
merged_xoff_cnt_32b_A_i	mgt_data_array ( 1 downto 0 )
merged_xoff_active_cnt_32b_A_i	mgt_data_array ( 1 downto 0 )
merged_xoff_assert_cnt_32b_A_i	mgt_data_array ( 1 downto 0 )
merged_xoff_cnt_32b_B_i	mgt_data_array ( 1 downto 0 )
merged_xoff_active_cnt_32b_B_i	mgt_data_array ( 1 downto 0 )
merged_xoff_assert_cnt_32b_B_i	mgt_data_array ( 1 downto 0 )
tob_fifo_tide_mark_A_bus_i	fifo_status_array ( 3 downto 0 )
tob_packet_tide_mark_A_bus_i	fifo_status_array ( 3 downto 0 )
tob_fifo_tide_mark_B_bus_i	fifo_status_array ( 3 downto 0 )
tob_packet_tide_mark_B_bus_i	fifo_status_array ( 3 downto 0 )
merged_fifo_tide_mark_A_bus_i	fifo_status_array ( 1 downto 0 )
merged_packet_tide_mark_A_bus_i	fifo_status_array ( 1 downto 0 )
merged_fifo_tide_mark_B_bus_i	fifo_status_array ( 1 downto 0 )
merged_packet_tide_mark_B_bus_i	fifo_status_array ( 1 downto 0 )
raw_fifo_tide_mark_bus_i	fifo_status_array ( 3 downto 0 )
raw_packet_tide_mark_bus_i	fifo_status_array ( 3 downto 0 )
TOB_packet_merged_cnt_A_bus_out_i	mgt_data_array ( 3 downto 0 )
TOB_packet_missing_cnt_A_bus_out_i	mgt_data_array ( 3 downto 0 )
debug_packet_created_cnt_A_bus_out_i	mgt_data_array ( 3 downto 0 )
TOB_packet_merged_cnt_B_bus_out_i	mgt_data_array ( 3 downto 0 )
TOB_packet_missing_cnt_B_bus_out_i	mgt_data_array ( 3 downto 0 )
debug_packet_created_cnt_B_bus_out_i	mgt_data_array ( 3 downto 0 )
Last_L1ID_merger_A_i	std_logic_vector ( 31 downto 0 )
Last_L1ID_merger_B_i	std_logic_vector ( 31 downto 0 )
L1A_cnt_merger_A_i	std_logic_vector ( 31 downto 0 )
L1A_cnt_merger_B_i	std_logic_vector ( 31 downto 0 )
tob_mgt_packet_received_cnt_bus_i	mgt_data_array ( 3 downto 0 )
tob_mgt_safe_mode_cnt_bus_i	mgt_data_array ( 3 downto 0 )
tob_mgt_packet_err_cnt_bus_i	mgt_data_array ( 3 downto 0 )
tob_mgt_length_err_cnt_bus_i	mgt_data_array ( 3 downto 0 )
tob_mgt_bcn_err_cnt_bus_i	mgt_data_array ( 3 downto 0 )
raw_mgt_packet_received_cnt_bus_i	mgt_data_array ( 3 downto 0 )
raw_mgt_safe_mode_cnt_bus_i	mgt_data_array ( 3 downto 0 )
raw_mgt_packet_err_cnt_bus_i	mgt_data_array ( 3 downto 0 )
raw_mgt_length_err_cnt_bus_i	mgt_data_array ( 3 downto 0 )
tob_mgt_last_l1id_bus_i	mgt_data_array ( 3 downto 0 )
raw_mgt_last_l1id_bus_i	mgt_data_array ( 3 downto 0 )
tob_mgt_last_error_l1id_bus_i	mgt_data_array ( 3 downto 0 )
raw_mgt_last_error_l1id_bus_i	mgt_data_array ( 3 downto 0 )
mux_l1id_valid_bus_i	std_logic_vector ( 1 downto 0 )
mux_l1id_bus_i	mgt_data_array ( 1 downto 0 )
mux_source_bus_i	std_logic_vector ( 7 downto 0 )
mux_source_a	integer range 0 to 15 := 0
mux_source_b	integer range 0 to 15 := 0
mux_a_pkt_bus_i	std_logic_vector ( 5 downto 0 )
mux_b_pkt_bus_i	std_logic_vector ( 5 downto 0 )
mux_a_pkt_cnt_bus_i	mgt_data_array ( 5 downto 0 )
mux_b_pkt_cnt_bus_i	mgt_data_array ( 5 downto 0 )
mux_a_last_l1id_bus_i	mgt_data_array ( 5 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
mux_b_last_l1id_bus_i	mgt_data_array ( 5 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
mux_active_bus_i	fifo_status_array ( 1 downto 0 )
mux_a_active_bus_i	fifo_status_array ( 5 downto 0 )
mux_b_active_bus_i	fifo_status_array ( 5 downto 0 )
mux_a_active_tide_mark_bus_i	fifo_status_array ( 5 downto 0 )
mux_b_active_tide_mark_bus_i	fifo_status_array ( 5 downto 0 )
mux_orbit_active_bus_i	fifo_status_array ( 1 downto 0 )
mux_orbit_active_tide_mark_bus_i	fifo_status_array ( 1 downto 0 )

Instantiations
u1_rdout_ipb_slave	rdout_ipb_slave <Entity rdout_ipb_slave>
u2_rdout_err_cnt	rdout_err_cnt <Entity rdout_err_cnt>
u3_monitoring_block	rdout_monitor <Entity rdout_monitor>
packet_tide_mark_block	packet_tide_mark_block <Entity packet_tide_mark_block>

Detailed Description

Definition at line 176 of file packet_status_block.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/packet_status_block.vhd