rdout_monitor Entity Reference

Control Readout FIFO level Monitor. More...

Inheritance diagram for rdout_monitor:

Entities
Behavioral	architecture
	Control Readout FIFO level Monitor. More...

Libraries
ieee
infrastructure_lib

Use Clauses
std_logic_1164
numeric_std
packet_mux_type	Package <packet_mux_type>

Ports
clk_320	in	std_logic
rst_xoff_cntr	in	std_logic
tob_fifo_prog_full_thresh_assert	in	std_logic_vector ( 15 downto 0 )
		BUSY TOB FIFO partial full flag thresholds.
tob_fifo_prog_full_thresh_negate	in	std_logic_vector ( 15 downto 0 )
raw_fifo_prog_full_thresh_assert	in	std_logic_vector ( 15 downto 0 )
		BUSY input RAW FIFO partial full flag assert thresholds.
raw_fifo_prog_full_thresh_negate	in	std_logic_vector ( 15 downto 0 )
tob_fifo_XOFF_thresh_assert	in	std_logic_vector ( 15 downto 0 )
		XOFF TOB FIFO partial full flag thresholds.
tob_fifo_XOFF_thresh_negate	in	std_logic_vector ( 15 downto 0 )
merged_fifo_XOFF_thresh_assert	in	std_logic_vector ( 15 downto 0 )
		XOFF merged FIFO partial full flag assert thresholds.
merged_fifo_XOFF_thresh_negate	in	std_logic_vector ( 15 downto 0 )
raw_fifo_XOFF_thresh_assert	in	std_logic_vector ( 15 downto 0 )
		XOFF input RAW FIFO partial full flag assert thresholds.
raw_fifo_XOFF_thresh_negate	in	std_logic_vector ( 15 downto 0 )
dbg_fifo_XOFF_thresh_assert	in	std_logic_vector ( 15 downto 0 )
		XOFF debug FIFO partial full flag assert thresholds.
dbg_fifo_XOFF_thresh_negate	in	std_logic_vector ( 15 downto 0 )
tob_fifo_fill_level_A_bus	in	fifo_status_array ( 3 downto 0 )
		TOB FIFO status block B XOFF & BUSY.
tob_fifo_fill_level_B_bus	in	fifo_status_array ( 3 downto 0 )
merged_fifo_fill_level_A_bus	in	fifo_status_array ( 1 downto 0 )
		Aurora merged_fifo status bits PAUSE.
merged_fifo_fill_level_B_bus	in	fifo_status_array ( 1 downto 0 )
raw_fifo_fill_level_bus	in	fifo_status_array ( 3 downto 0 )
		Raw FIFO status block XOFF & BUSY.
fifo_bc_count	out	std_logic_vector ( 31 downto 0 )
tob_busy_cnt_32b_A	out	mgt_data_array ( 3 downto 0 )
tob_busy_cnt_32b_B	out	mgt_data_array ( 3 downto 0 )
raw_busy_cnt_32b	out	mgt_data_array ( 3 downto 0 )
tob_busy_active_cnt_32b_A	out	mgt_data_array ( 3 downto 0 )
tob_busy_active_cnt_32b_B	out	mgt_data_array ( 3 downto 0 )
raw_busy_active_cnt_32b	out	mgt_data_array ( 3 downto 0 )
tob_busy_assert_cnt_32b_A	out	mgt_data_array ( 3 downto 0 )
tob_busy_assert_cnt_32b_B	out	mgt_data_array ( 3 downto 0 )
raw_busy_assert_cnt_32b	out	mgt_data_array ( 3 downto 0 )
tob_xoff_cnt_32b_A	out	mgt_data_array ( 3 downto 0 )
tob_xoff_cnt_32b_B	out	mgt_data_array ( 3 downto 0 )
raw_xoff_cnt_32b	out	mgt_data_array ( 3 downto 0 )
merged_xoff_cnt_32b_A	out	mgt_data_array ( 1 downto 0 )
merged_xoff_cnt_32b_B	out	mgt_data_array ( 1 downto 0 )
tob_xoff_active_cnt_32b_A	out	mgt_data_array ( 3 downto 0 )
tob_xoff_active_cnt_32b_B	out	mgt_data_array ( 3 downto 0 )
raw_xoff_active_cnt_32b	out	mgt_data_array ( 3 downto 0 )
merged_xoff_active_cnt_32b_A	out	mgt_data_array ( 1 downto 0 )
merged_xoff_active_cnt_32b_B	out	mgt_data_array ( 1 downto 0 )
tob_xoff_assert_cnt_32b_A	out	mgt_data_array ( 3 downto 0 )
tob_xoff_assert_cnt_32b_B	out	mgt_data_array ( 3 downto 0 )
raw_xoff_assert_cnt_32b	out	mgt_data_array ( 3 downto 0 )
merged_xoff_assert_cnt_32b_A	out	mgt_data_array ( 1 downto 0 )
merged_xoff_assert_cnt_32b_B	out	mgt_data_array ( 1 downto 0 )
tob_mgt_xoff_bus	out	std_logic_vector ( 3 downto 0 )
raw_mgt_xoff_bus	out	std_logic_vector ( 3 downto 0 )
tob_busy_bus	out	std_logic_vector ( 3 downto 0 )
raw_busy_bus	out	std_logic_vector ( 3 downto 0 )
Block_A_pause	out	std_logic_vector ( 1 downto 0 )
Block_B_pause	out	std_logic_vector ( 1 downto 0 )

Detailed Description

Control Readout FIFO level Monitor.

This module has FIFO Partial Full assert and negate values as input It then generates XOFF, BUSY and PAUSE signals as required.

Author

Saeed Taghavi

Definition at line 17 of file rdout_monitor.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/rdout_monitor.vhd