eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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rdout_monitor.vhd
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1 
8 
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12 
13 library infrastructure_lib;
14 use infrastructure_lib.packet_mux_type.all;
15 
17 entity rdout_monitor is
18  port (
19  clk_320 : in std_logic;
20  rst_xoff_cntr : in std_logic;
21 
23  tob_fifo_prog_full_thresh_assert : in std_logic_vector(15 downto 0);
24  tob_fifo_prog_full_thresh_negate : in std_logic_vector(15 downto 0);
25 
27  raw_fifo_prog_full_thresh_assert : in std_logic_vector(15 downto 0);
28  raw_fifo_prog_full_thresh_negate : in std_logic_vector(15 downto 0);
29 
31  tob_fifo_XOFF_thresh_assert : in std_logic_vector(15 downto 0);
32  tob_fifo_XOFF_thresh_negate : in std_logic_vector(15 downto 0);
33 
35  merged_fifo_XOFF_thresh_assert : in std_logic_vector(15 downto 0);
36  merged_fifo_XOFF_thresh_negate : in std_logic_vector(15 downto 0);
37 
39  raw_fifo_XOFF_thresh_assert : in std_logic_vector(15 downto 0);
40  raw_fifo_XOFF_thresh_negate : in std_logic_vector(15 downto 0);
41 
43  dbg_fifo_XOFF_thresh_assert : in std_logic_vector(15 downto 0);
44  dbg_fifo_XOFF_thresh_negate : in std_logic_vector(15 downto 0);
45 
47  tob_fifo_fill_level_A_bus : in fifo_status_array(3 downto 0); -- array of 16-bits
48  tob_fifo_fill_level_B_bus : in fifo_status_array(3 downto 0);
50  merged_fifo_fill_level_A_bus: in fifo_status_array(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1) 16-bits inputs
51  merged_fifo_fill_level_B_bus: in fifo_status_array(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1) 16-bits inputs
53  raw_fifo_fill_level_bus : in fifo_status_array(3 downto 0); -- 16-bits
54 
55  fifo_bc_count : out std_logic_vector(31 downto 0);
56 
57  tob_busy_cnt_32b_A : out mgt_data_array(3 downto 0); -- 32-bits
58  tob_busy_cnt_32b_B : out mgt_data_array(3 downto 0); -- 32-bits
59  raw_busy_cnt_32b : out mgt_data_array(3 downto 0); -- 32-bits
60 
61  tob_busy_active_cnt_32b_A : out mgt_data_array(3 downto 0); -- 32-bits
62  tob_busy_active_cnt_32b_B : out mgt_data_array(3 downto 0); -- 32-bits
63  raw_busy_active_cnt_32b : out mgt_data_array(3 downto 0); -- 32-bits
64 
65  tob_busy_assert_cnt_32b_A : out mgt_data_array(3 downto 0); -- 32-bits
66  tob_busy_assert_cnt_32b_B : out mgt_data_array(3 downto 0); -- 32-bits
67  raw_busy_assert_cnt_32b : out mgt_data_array(3 downto 0); -- 32-bits
68 
69  tob_xoff_cnt_32b_A : out mgt_data_array(3 downto 0); -- 32-bits
70  tob_xoff_cnt_32b_B : out mgt_data_array(3 downto 0); -- 32-bits
71  raw_xoff_cnt_32b : out mgt_data_array(3 downto 0); -- 32-bits
72  merged_xoff_cnt_32b_A : out mgt_data_array(1 downto 0); -- 32-bits
73  merged_xoff_cnt_32b_B : out mgt_data_array(1 downto 0); -- 32-bits
74 
75  tob_xoff_active_cnt_32b_A : out mgt_data_array(3 downto 0); -- 32-bits
76  tob_xoff_active_cnt_32b_B : out mgt_data_array(3 downto 0); -- 32-bits
77  raw_xoff_active_cnt_32b : out mgt_data_array(3 downto 0); -- 32-bits
78  merged_xoff_active_cnt_32b_A: out mgt_data_array(1 downto 0); -- 32-bits
79  merged_xoff_active_cnt_32b_B: out mgt_data_array(1 downto 0); -- 32-bits
80 
81  tob_xoff_assert_cnt_32b_A : out mgt_data_array(3 downto 0); -- 32-bits
82  tob_xoff_assert_cnt_32b_B : out mgt_data_array(3 downto 0); -- 32-bits
83  raw_xoff_assert_cnt_32b : out mgt_data_array(3 downto 0); -- 32-bits
84  merged_xoff_assert_cnt_32b_A: out mgt_data_array(1 downto 0); -- 32-bits
85  merged_xoff_assert_cnt_32b_B: out mgt_data_array(1 downto 0); -- 32-bits
86 
87 -- MGT flow control
88  tob_mgt_xoff_bus : out std_logic_vector(3 downto 0); -- to process FPGAs
89  raw_mgt_xoff_bus : out std_logic_vector(3 downto 0);
90 -- BUSY control
91  tob_busy_bus : out std_logic_vector(3 downto 0);
92  raw_busy_bus : out std_logic_vector(3 downto 0);
93 -- Merging block flow ontol
94  Block_A_pause : out std_logic_vector(1 downto 0);
95  Block_B_pause : out std_logic_vector(1 downto 0)
96  );
97 end rdout_monitor;
98 
100 architecture Behavioral of rdout_monitor is
101 
102  signal busy_bus, busy_bus_a, busy_bus_b, busy_count_bus, busy_reset_bus, busy_assert_bus: std_logic_vector(11 downto 0);
103  signal xoff_bus, xoff_bus_a, xoff_bus_b, xoff_count_bus, xoff_reset_bus, xoff_assert_bus: std_logic_vector(15 downto 0);
104  signal fifo_bc_count_35b: std_logic_vector(34 downto 0);
105  signal busy_cnt_35b, busy_active_cnt_35b: cntr_35b_array(11 downto 0);
106  signal xoff_cnt_35b, xoff_active_cnt_35b: cntr_35b_array(15 downto 0);
107  signal busy_assert_cnt_32b: mgt_data_array(11 downto 0);
108  signal xoff_assert_cnt_32b: mgt_data_array(15 downto 0);
109  signal merge_debug_XOFF_thresh_assert, merge_debug_XOFF_thresh_negate: fifo_status_array(1 downto 0);
110 
111 begin
112 
113  merge_debug_XOFF_thresh_assert <= dbg_fifo_XOFF_thresh_assert & merged_fifo_XOFF_thresh_assert;
114  merge_debug_XOFF_thresh_negate <= dbg_fifo_XOFF_thresh_negate & merged_fifo_XOFF_thresh_negate;
115 
116  tob_busy_bus <= busy_bus(3 downto 0) OR busy_bus(7 downto 4);
117  raw_busy_bus <= busy_bus(11 downto 8);
118 
119  tob_mgt_xoff_bus <= xoff_bus(3 downto 0) OR xoff_bus(7 downto 4);
120  raw_mgt_xoff_bus <= xoff_bus(11 downto 8);
121  Block_A_pause <= xoff_bus(13 downto 12);
122  Block_B_pause <= xoff_bus(15 downto 14);
123 
124 bc_count : entity infrastructure_lib.cntr_generic
125  generic map (width => 35, WRAPAROUND => False)
126  port map (
127  CE => '1',
128  CLK => clk_320,
129  RST => rst_xoff_cntr,
130  Q => fifo_bc_count_35b
131  );
132 
133  fifo_bc_count <= fifo_bc_count_35b(34 downto 3);
134 
135 GENERATE_1 : for i in 0 to 3 generate
136  tob_busy_a : process (clk_320)
137  begin
138  if rising_edge (clk_320) then
139  if unsigned(tob_fifo_fill_level_A_bus(i)) >= unsigned(tob_fifo_prog_full_thresh_assert) then
140  busy_bus(i) <= '1' ; -- assert TOB BUSY flags
141  elsif unsigned(tob_fifo_fill_level_A_bus(i)) < unsigned(tob_fifo_prog_full_thresh_negate) then
142  busy_bus(i) <= '0' ; -- negate TOB BUSY flags
143  end if;
144  end if;
145  end process;
146 
147  tob_busy_b : process (clk_320)
148  begin
149  if rising_edge (clk_320) then
150  if unsigned(tob_fifo_fill_level_B_bus(i)) >= unsigned(tob_fifo_prog_full_thresh_assert) then
151  busy_bus(i+4) <= '1' ; -- assert TOB BUSY flags
152  elsif unsigned(tob_fifo_fill_level_B_bus(i)) < unsigned(tob_fifo_prog_full_thresh_negate) then
153  busy_bus(i+4) <= '0' ; -- negate TOB BUSY flags
154  end if;
155  end if;
156  end process;
157 
158  raw_busy : process (clk_320)
159  begin
160  if rising_edge (clk_320) then
161  if unsigned(raw_fifo_fill_level_bus(i)) >= unsigned(raw_fifo_prog_full_thresh_assert) then
162  busy_bus(i+8) <= '1' ; -- assert RAW BUSY flags
163  elsif unsigned(raw_fifo_fill_level_bus(i)) < unsigned(raw_fifo_prog_full_thresh_negate) then
164  busy_bus(i+8) <= '0' ; -- negate RAW BUSY flags
165  end if;
166  end if;
167  end process;
168 
169  tob_xoff_a : process (clk_320)
170  begin
171  if rising_edge (clk_320) then
172  if unsigned(tob_fifo_fill_level_A_bus(i)) >= unsigned(tob_fifo_xoff_thresh_assert) then
173  xoff_bus(i) <= '1' ; -- assert TOB XOFF flags
174  elsif unsigned(tob_fifo_fill_level_A_bus(i)) < unsigned(tob_fifo_xoff_thresh_negate) then
175  xoff_bus(i) <= '0' ; -- negate TOB XOFF flags
176  end if;
177  end if;
178  end process;
179 
180  tob_xoff_b : process (clk_320)
181  begin
182  if rising_edge (clk_320) then
183  if unsigned(tob_fifo_fill_level_B_bus(i)) >= unsigned(tob_fifo_xoff_thresh_assert) then
184  xoff_bus(i+4) <= '1' ; -- assert TOB XOFF flags
185  elsif unsigned(tob_fifo_fill_level_B_bus(i)) < unsigned(tob_fifo_xoff_thresh_negate) then
186  xoff_bus(i+4) <= '0' ; -- negate TOB XOFF flags
187  end if;
188  end if;
189  end process;
190 
191  raw_xoff : process (clk_320)
192  begin
193  if rising_edge (clk_320) then
194  if unsigned(raw_fifo_fill_level_bus(i)) >= unsigned(raw_fifo_xoff_thresh_assert) then
195  xoff_bus(i+8) <= '1' ; -- assert RAW XOFF flags
196  elsif unsigned(raw_fifo_fill_level_bus(i)) < unsigned(raw_fifo_xoff_thresh_negate) then
197  xoff_bus(i+8) <= '0' ; -- negate RAW XOFF flags
198  end if;
199  end if;
200  end process;
201 
202 -- map counters onto outputs, truncating tick counters down to BC
203  tob_busy_cnt_32b_A(i) <= busy_cnt_35b(i)(34 downto 3);
204  tob_busy_cnt_32b_B(i) <= busy_cnt_35b(i+4)(34 downto 3);
205  raw_busy_cnt_32b(i) <= busy_cnt_35b(i+8)(34 downto 3);
206 
207  tob_busy_active_cnt_32b_A(i) <= busy_active_cnt_35b(i)(34 downto 3);
208  tob_busy_active_cnt_32b_B(i) <= busy_active_cnt_35b(i+4)(34 downto 3);
209  raw_busy_active_cnt_32b(i) <= busy_active_cnt_35b(i+8)(34 downto 3);
210 
211  tob_busy_assert_cnt_32b_A(i) <= busy_assert_cnt_32b(i);
212  tob_busy_assert_cnt_32b_B(i) <= busy_assert_cnt_32b(i+4);
213  raw_busy_assert_cnt_32b(i) <= busy_assert_cnt_32b(i+8);
214 
215  tob_xoff_cnt_32b_A(i) <= xoff_cnt_35b(i)(34 downto 3);
216  tob_xoff_cnt_32b_B(i) <= xoff_cnt_35b(i+4)(34 downto 3);
217  raw_xoff_cnt_32b(i) <= xoff_cnt_35b(i+8)(34 downto 3);
218 
219  tob_xoff_active_cnt_32b_A(i) <= xoff_active_cnt_35b(i)(34 downto 3);
220  tob_xoff_active_cnt_32b_B(i) <= xoff_active_cnt_35b(i+4)(34 downto 3);
221  raw_xoff_active_cnt_32b(i) <= xoff_active_cnt_35b(i+8)(34 downto 3);
222 
223  tob_xoff_assert_cnt_32b_A(i) <= xoff_assert_cnt_32b(i);
224  tob_xoff_assert_cnt_32b_B(i) <= xoff_assert_cnt_32b(i+4);
225  raw_xoff_assert_cnt_32b(i) <= xoff_assert_cnt_32b(i+8);
226 end generate GENERATE_1;
227 
228 GENERATE_2 : for i in 0 to 1 generate
229  merged_xoff_a : process (clk_320)
230  begin
231  if rising_edge (clk_320) then
232  if unsigned(merged_fifo_fill_level_A_bus(i)) > unsigned(merge_debug_XOFF_thresh_assert(i)) then
233  xoff_bus(i+12) <= '1' ; -- assert Merged XOFF flags
234  elsif unsigned(merged_fifo_fill_level_A_bus(i)) < unsigned(merge_debug_XOFF_thresh_negate(i)) then
235  xoff_bus(i+12) <= '0' ; -- negate Merged XOFF flags
236  end if;
237  end if;
238  end process;
239 
240  merged_xoff_b : process (clk_320)
241  begin
242  if rising_edge (clk_320) then
243  if unsigned(merged_fifo_fill_level_B_bus(i)) > unsigned(merge_debug_XOFF_thresh_assert(i)) then
244  xoff_bus(i+14) <= '1' ; -- assert Merged XOFF flags
245  elsif unsigned(merged_fifo_fill_level_B_bus(i)) < unsigned(merge_debug_XOFF_thresh_negate(i)) then
246  xoff_bus(i+14) <= '0' ; -- negate Merged XOFF flags
247  end if;
248  end if;
249  end process;
250 
251 -- map counters onto outputs, truncating tick counters down to BC
252  merged_xoff_cnt_32b_A(i) <= xoff_cnt_35b(i+12)(34 downto 3);
253  merged_xoff_cnt_32b_B(i) <= xoff_cnt_35b(i+14)(34 downto 3);
254 
255  merged_xoff_active_cnt_32b_A(i) <= xoff_active_cnt_35b(i+12)(34 downto 3);
256  merged_xoff_active_cnt_32b_B(i) <= xoff_active_cnt_35b(i+14)(34 downto 3);
257 
258  merged_xoff_assert_cnt_32b_A(i) <= xoff_assert_cnt_32b(i+12);
259  merged_xoff_assert_cnt_32b_B(i) <= xoff_assert_cnt_32b(i+14);
260 end generate GENERATE_2;
261 
262 busy_xoff_registers: process(clk_320)
263 begin
264  if rising_edge(clk_320) then
265  xoff_bus_a <= xoff_bus;
266  xoff_bus_b <= xoff_bus_a;
267  xoff_count_bus <= xoff_bus_b; -- and delay the counters to be in sync after the reset for the active counters
268  busy_bus_a <= busy_bus;
269  busy_bus_b <= busy_bus_a;
270  busy_count_bus <= busy_bus_b; -- and delay the counters to be in sync after the reset for the active counters
271  if (rst_xoff_cntr = '1') then
272  xoff_reset_bus <= (Others => '1');
273  xoff_assert_bus <= (Others => '0');
274  busy_reset_bus <= (Others => '1');
275  busy_assert_bus <= (Others => '0');
276  else -- generate a reset for the active counters from transition from 0 to 1
277  xoff_reset_bus <= xoff_bus and not xoff_bus_a;
278  xoff_assert_bus <= xoff_bus and not xoff_bus_a;
279  busy_reset_bus <= busy_bus and not busy_bus_a;
280  busy_assert_bus <= busy_bus and not busy_bus_a;
281  end if;
282  end if;
283 end process busy_xoff_registers;
284 
285 GENERATE_3 : for i in 0 to 11 generate
286  busy_count : entity infrastructure_lib.cntr_generic
287  generic map (width => 35, WRAPAROUND => False)
288  port map (
289  CE => busy_count_bus(i),
290  CLK => clk_320,
291  RST => rst_xoff_cntr,
292  Q => busy_cnt_35b(i));
293 
294  busy_active_count : entity infrastructure_lib.cntr_generic
295  generic map (width => 35, WRAPAROUND => False)
296  port map (
297  CE => busy_count_bus(i),
298  CLK => clk_320,
299  RST => busy_reset_bus(i),
300  Q => busy_active_cnt_35b(i));
301 
302  busy_assert_counter : entity infrastructure_lib.cntr_generic
303  generic map (width => 32, WRAPAROUND => False)
304  port map (
305  CE => busy_assert_bus(i),
306  CLK => clk_320,
307  RST => rst_xoff_cntr,
308  Q => busy_assert_cnt_32b(i));
309 end generate GENERATE_3;
310 
311 GENERATE_4 : for i in 0 to 15 generate
312  xoff_count : entity infrastructure_lib.cntr_generic
313  generic map (width => 35, WRAPAROUND => False)
314  port map (
315  CE => xoff_count_bus(i),
316  CLK => clk_320,
317  RST => rst_xoff_cntr,
318  Q => xoff_cnt_35b(i));
319 
320  xoff_active_count : entity infrastructure_lib.cntr_generic
321  generic map (width => 35, WRAPAROUND => False)
322  port map (
323  CE => xoff_count_bus(i),
324  CLK => clk_320,
325  RST => xoff_reset_bus(i),
326  Q => xoff_active_cnt_35b(i));
327 
328  xoff_assert_counter : entity infrastructure_lib.cntr_generic
329  generic map (width => 32, WRAPAROUND => False)
330  port map (
331  CE => xoff_assert_bus(i),
332  CLK => clk_320,
333  RST => rst_xoff_cntr,
334  Q => xoff_assert_cnt_32b(i));
335 end generate GENERATE_4;
336 
337 end Behavioral;
cntr_generic
Generic Counter for process FPGA.
Definition: cntr_generic.vhd:16
cntr_generic.CLK
in CLK STD_LOGIC
Clock signal input.
Definition: cntr_generic.vhd:25
cntr_generic.CE
in CE STD_LOGIC
Enable signal input.
Definition: cntr_generic.vhd:23
cntr_generic.Q
out Q STD_LOGIC_VECTOR( width- 1 downto 0)
Counter Output signal.
Definition: cntr_generic.vhd:30
cntr_generic.RST
in RST STD_LOGIC
Reset signal input.
Definition: cntr_generic.vhd:27
packet_mux_type
Definition: packet_mux_type.vhd:4
rdout_monitor.Behavioral
Control Readout FIFO level Monitor.
Definition: rdout_monitor.vhd:100
rdout_monitor
Control Readout FIFO level Monitor.
Definition: rdout_monitor.vhd:17
rdout_monitor.tob_fifo_fill_level_A_bus
in tob_fifo_fill_level_A_bus fifo_status_array( 3 downto 0)
TOB FIFO status block B XOFF & BUSY.
Definition: rdout_monitor.vhd:47
rdout_monitor.dbg_fifo_XOFF_thresh_assert
in dbg_fifo_XOFF_thresh_assert std_logic_vector( 15 downto 0)
XOFF debug FIFO partial full flag assert thresholds.
Definition: rdout_monitor.vhd:43
rdout_monitor.merged_fifo_XOFF_thresh_assert
in merged_fifo_XOFF_thresh_assert std_logic_vector( 15 downto 0)
XOFF merged FIFO partial full flag assert thresholds.
Definition: rdout_monitor.vhd:35
rdout_monitor.raw_fifo_prog_full_thresh_assert
in raw_fifo_prog_full_thresh_assert std_logic_vector( 15 downto 0)
BUSY input RAW FIFO partial full flag assert thresholds.
Definition: rdout_monitor.vhd:27
rdout_monitor.raw_fifo_fill_level_bus
in raw_fifo_fill_level_bus fifo_status_array( 3 downto 0)
Raw FIFO status block XOFF & BUSY.
Definition: rdout_monitor.vhd:53
rdout_monitor.tob_fifo_XOFF_thresh_assert
in tob_fifo_XOFF_thresh_assert std_logic_vector( 15 downto 0)
XOFF TOB FIFO partial full flag thresholds.
Definition: rdout_monitor.vhd:31
rdout_monitor.merged_fifo_fill_level_A_bus
in merged_fifo_fill_level_A_bus fifo_status_array( 1 downto 0)
Aurora merged_fifo status bits PAUSE.
Definition: rdout_monitor.vhd:50
rdout_monitor.raw_fifo_XOFF_thresh_assert
in raw_fifo_XOFF_thresh_assert std_logic_vector( 15 downto 0)
XOFF input RAW FIFO partial full flag assert thresholds.
Definition: rdout_monitor.vhd:39
rdout_monitor.tob_fifo_prog_full_thresh_assert
in tob_fifo_prog_full_thresh_assert std_logic_vector( 15 downto 0)
BUSY TOB FIFO partial full flag thresholds.
Definition: rdout_monitor.vhd:23
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