Control Readout FIFO level Monitor. More...

Signals
busy_bus	std_logic_vector ( 11 downto 0 )
busy_bus_a	std_logic_vector ( 11 downto 0 )
busy_bus_b	std_logic_vector ( 11 downto 0 )
busy_count_bus	std_logic_vector ( 11 downto 0 )
busy_reset_bus	std_logic_vector ( 11 downto 0 )
busy_assert_bus	std_logic_vector ( 11 downto 0 )
xoff_bus	std_logic_vector ( 15 downto 0 )
xoff_bus_a	std_logic_vector ( 15 downto 0 )
xoff_bus_b	std_logic_vector ( 15 downto 0 )
xoff_count_bus	std_logic_vector ( 15 downto 0 )
xoff_reset_bus	std_logic_vector ( 15 downto 0 )
xoff_assert_bus	std_logic_vector ( 15 downto 0 )
fifo_bc_count_35b	std_logic_vector ( 34 downto 0 )
busy_cnt_35b	cntr_35b_array ( 11 downto 0 )
busy_active_cnt_35b	cntr_35b_array ( 11 downto 0 )
xoff_cnt_35b	cntr_35b_array ( 15 downto 0 )
xoff_active_cnt_35b	cntr_35b_array ( 15 downto 0 )
busy_assert_cnt_32b	mgt_data_array ( 11 downto 0 )
xoff_assert_cnt_32b	mgt_data_array ( 15 downto 0 )
merge_debug_XOFF_thresh_assert	fifo_status_array ( 1 downto 0 )
merge_debug_XOFF_thresh_negate	fifo_status_array ( 1 downto 0 )

Instantiations
bc_count	cntr_generic <Entity cntr_generic>
busy_count	cntr_generic <Entity cntr_generic>
busy_active_count	cntr_generic <Entity cntr_generic>
busy_assert_counter	cntr_generic <Entity cntr_generic>
xoff_count	cntr_generic <Entity cntr_generic>
xoff_active_count	cntr_generic <Entity cntr_generic>
xoff_assert_counter	cntr_generic <Entity cntr_generic>

Detailed Description

Control Readout FIFO level Monitor.

This module has FIFO Partial Full assert and negate values as input It then generates XOFF, BUSY and PAUSE signals as required.

Definition at line 100 of file rdout_monitor.vhd.

The documentation for this class was generated from the following file:

Processes