rdout_ipb_slave Entity Reference

Control FPGA data_path slave registers. More...

Inheritance diagram for rdout_ipb_slave:

Entities
Behavioral	architecture
	Control FPGA data_path slave registers. More...

Libraries
IEEE
ipbus_lib
infrastructure_lib

Use Clauses
STD_LOGIC_1164
numeric_std
ipbus
packet_mux_type	Package <packet_mux_type>
ipbus_decode_efex_cntrl_data_path	Package <ipbus_decode_efex_cntrl_data_path>

Generics
TOB_FIFO_MAX_ADDR_WIDTH	positive := 12
MERGED_FIFO_MAX_ADDR_WIDTH	positive := 11
	address bus width of TOB FIFO RAM in packet_fifo_block for each Processor FPGA
RAW_FIFO_MAX_ADDR_WIDTH	positive := 11
	address bus width of merged FIFO RAMs after TOB merging
PACKET_MAX_WIDTH	positive := 8
	address bus width of RAW FIFO RAM in packet_fifo_block for each Processor FPGA address bus width of maximum input packet (i.e. 8 implies 256 64 bit words), merged packets can be 4 times larger

Ports
clk_320	in	std_logic
ipb_rst	in	std_logic
		IPBus Reset input.
ipb_clk	in	std_logic
		IPBus Clock input.
IPb_in	in	ipb_wbus
		IPBus input bus going from master to slaves.
IPb_out	out	ipb_rbus
		IPBus output bus going from slaves to master.
ipbus_out_tob_mgt_wbus_array	out	ipb_wbus_array ( 3 downto 0 )
		MGT TOB input spy RAMs.
ipbus_in_tob_mgt_rbus_array	in	ipb_rbus_array ( 3 downto 0 )
ipbus_out_raw_mgt_wbus_array	out	ipb_wbus_array ( 3 downto 0 )
		MGT raw input spy RAMs.
ipbus_in_raw_mgt_rbus_array	in	ipb_rbus_array ( 3 downto 0 )
ipbus_out_merger_spy_wbus_array	out	ipb_wbus_array ( 1 downto 0 )
		Merger debug spy RAMs.
ipbus_in_merger_spy_rbus_array	in	ipb_rbus_array ( 1 downto 0 )
ipbus_out_built_fifo_wbus_array	out	ipb_wbus_array ( 1 downto 0 )
		Aurora output spy RAMs.
ipbus_in_built_fifo_rbus_array	in	ipb_rbus_array ( 1 downto 0 )
bcr_320	in	std_logic
		Control registers.
ecr_320	in	std_logic
readout_delay	out	std_logic_vector ( 31 downto 0 )
counter_control	out	std_logic_vector ( 31 downto 0 )
spy_ram_rst_wr_addr	out	std_logic_vector ( 31 downto 0 )
wraparound_enable	out	std_logic_vector ( 31 downto 0 )
tob_fifo_prog_full_thresh_assert	out	std_logic_vector ( 15 downto 0 )
		BUSY FIFO partial full flag thresholds.
tob_fifo_prog_full_thresh_negate	out	std_logic_vector ( 15 downto 0 )
raw_fifo_prog_full_thresh_assert	out	std_logic_vector ( 15 downto 0 )
raw_fifo_prog_full_thresh_negate	out	std_logic_vector ( 15 downto 0 )
tob_fifo_XOFF_thresh_assert	out	std_logic_vector ( 15 downto 0 )
		XOFF FIFO partial full flag thresholds.
tob_fifo_XOFF_thresh_negate	out	std_logic_vector ( 15 downto 0 )
raw_fifo_XOFF_thresh_assert	out	std_logic_vector ( 15 downto 0 )
raw_fifo_XOFF_thresh_negate	out	std_logic_vector ( 15 downto 0 )
merged_fifo_XOFF_thresh_assert	out	std_logic_vector ( 15 downto 0 )
merged_fifo_XOFF_thresh_negate	out	std_logic_vector ( 15 downto 0 )
dbg_fifo_XOFF_thresh_assert	out	std_logic_vector ( 15 downto 0 )
dbg_fifo_XOFF_thresh_negate	out	std_logic_vector ( 15 downto 0 )
tob_mgt_packet_received_cnt_bus	in	mgt_data_array ( 3 downto 0 )
tob_mgt_safe_mode_cnt_bus	in	mgt_data_array ( 3 downto 0 )
tob_mgt_packet_err_cnt_bus	in	mgt_data_array ( 3 downto 0 )
tob_mgt_length_err_cnt_bus	in	mgt_data_array ( 3 downto 0 )
tob_mgt_bcn_err_cnt_bus	in	mgt_data_array ( 3 downto 0 )
tob_mgt_last_l1id_bus	in	mgt_data_array ( 3 downto 0 )
tob_mgt_last_error_l1id_bus	in	mgt_data_array ( 3 downto 0 )
raw_mgt_packet_received_cnt_bus	in	mgt_data_array ( 3 downto 0 )
raw_mgt_safe_mode_cnt_bus	in	mgt_data_array ( 3 downto 0 )
raw_mgt_packet_err_cnt_bus	in	mgt_data_array ( 3 downto 0 )
raw_mgt_length_err_cnt_bus	in	mgt_data_array ( 3 downto 0 )
raw_mgt_last_l1id_bus	in	mgt_data_array ( 3 downto 0 )
raw_mgt_last_error_l1id_bus	in	mgt_data_array ( 3 downto 0 )
tob_fifo_fill_level_A_bus	in	fifo_status_array ( 3 downto 0 )
tob_packet_count_A_bus	in	fifo_status_array ( 3 downto 0 )
tob_fifo_tide_mark_A_bus	in	fifo_status_array ( 3 downto 0 )
tob_packet_tide_mark_A_bus	in	fifo_status_array ( 3 downto 0 )
tob_fifo_err_cnt_A_bus	in	mgt_data_array ( 3 downto 0 )
tob_fifo_fill_level_B_bus	in	fifo_status_array ( 3 downto 0 )
tob_packet_count_B_bus	in	fifo_status_array ( 3 downto 0 )
tob_fifo_tide_mark_B_bus	in	fifo_status_array ( 3 downto 0 )
tob_packet_tide_mark_B_bus	in	fifo_status_array ( 3 downto 0 )
tob_fifo_err_cnt_B_bus	in	mgt_data_array ( 3 downto 0 )
merged_fifo_fill_level_A_bus	in	fifo_status_array ( 1 downto 0 )
merged_packet_count_A_bus	in	fifo_status_array ( 1 downto 0 )
merged_fifo_tide_mark_A_bus	in	fifo_status_array ( 1 downto 0 )
merged_packet_tide_mark_A_bus	in	fifo_status_array ( 1 downto 0 )
merged_fifo_err_cnt_A_bus	in	mgt_data_array ( 1 downto 0 )
merged_fifo_fill_level_B_bus	in	fifo_status_array ( 1 downto 0 )
merged_packet_count_B_bus	in	fifo_status_array ( 1 downto 0 )
merged_fifo_tide_mark_B_bus	in	fifo_status_array ( 1 downto 0 )
merged_packet_tide_mark_B_bus	in	fifo_status_array ( 1 downto 0 )
merged_fifo_err_cnt_B_bus	in	mgt_data_array ( 1 downto 0 )
raw_fifo_fill_level_bus	in	fifo_status_array ( 3 downto 0 )
raw_packet_count_bus	in	fifo_status_array ( 3 downto 0 )
raw_fifo_tide_mark_bus	in	fifo_status_array ( 3 downto 0 )
raw_packet_tide_mark_bus	in	fifo_status_array ( 3 downto 0 )
raw_fifo_err_cnt_bus	in	mgt_data_array ( 3 downto 0 )
L1A_cnt_merger_A	in	std_logic_vector ( 31 downto 0 )
L1A_cnt_merger_B	in	std_logic_vector ( 31 downto 0 )
Last_L1ID_merger_A	in	std_logic_vector ( 31 downto 0 )
Last_L1ID_merger_B	in	std_logic_vector ( 31 downto 0 )
TOB_packet_merged_cnt_A_bus	in	mgt_data_array ( 3 downto 0 )
TOB_packet_missing_cnt_A_bus	in	mgt_data_array ( 3 downto 0 )
debug_packet_created_cnt_A_bus	in	mgt_data_array ( 3 downto 0 )
TOB_packet_merged_cnt_B_bus	in	mgt_data_array ( 3 downto 0 )
TOB_packet_missing_cnt_B_bus	in	mgt_data_array ( 3 downto 0 )
debug_packet_created_cnt_B_bus	in	mgt_data_array ( 3 downto 0 )
mux_orbit_active_bus	in	fifo_status_array ( 1 downto 0 )
mux_orbit_active_tide_mark_bus	in	fifo_status_array ( 1 downto 0 )
mux_a_active_bus	in	fifo_status_array ( 5 downto 0 )
mux_b_active_bus	in	fifo_status_array ( 5 downto 0 )
mux_a_active_tide_mark_bus	in	fifo_status_array ( 5 downto 0 )
mux_b_active_tide_mark_bus	in	fifo_status_array ( 5 downto 0 )
mux_a_pkt_cnt_bus	in	mgt_data_array ( 5 downto 0 )
mux_b_pkt_cnt_bus	in	mgt_data_array ( 5 downto 0 )
mux_a_last_l1id_bus	in	mgt_data_array ( 5 downto 0 )
mux_b_last_l1id_bus	in	mgt_data_array ( 5 downto 0 )
fifo_bc_count	in	std_logic_vector ( 31 downto 0 )
tob_busy_cnt_32b_A	in	mgt_data_array ( 3 downto 0 )
tob_busy_cnt_32b_B	in	mgt_data_array ( 3 downto 0 )
raw_busy_cnt_32b	in	mgt_data_array ( 3 downto 0 )
tob_busy_active_cnt_32b_A	in	mgt_data_array ( 3 downto 0 )
tob_busy_active_cnt_32b_B	in	mgt_data_array ( 3 downto 0 )
raw_busy_active_cnt_32b	in	mgt_data_array ( 3 downto 0 )
tob_busy_assert_cnt_32b_A	in	mgt_data_array ( 3 downto 0 )
tob_busy_assert_cnt_32b_B	in	mgt_data_array ( 3 downto 0 )
raw_busy_assert_cnt_32b	in	mgt_data_array ( 3 downto 0 )
tob_xoff_cnt_32b_A	in	mgt_data_array ( 3 downto 0 )
tob_xoff_cnt_32b_B	in	mgt_data_array ( 3 downto 0 )
raw_xoff_cnt_32b	in	mgt_data_array ( 3 downto 0 )
merged_xoff_cnt_32b_A	in	mgt_data_array ( 1 downto 0 )
merged_xoff_cnt_32b_B	in	mgt_data_array ( 1 downto 0 )
tob_xoff_active_cnt_32b_A	in	mgt_data_array ( 3 downto 0 )
tob_xoff_active_cnt_32b_B	in	mgt_data_array ( 3 downto 0 )
raw_xoff_active_cnt_32b	in	mgt_data_array ( 3 downto 0 )
merged_xoff_active_cnt_32b_A	in	mgt_data_array ( 1 downto 0 )
merged_xoff_active_cnt_32b_B	in	mgt_data_array ( 1 downto 0 )
tob_xoff_assert_cnt_32b_A	in	mgt_data_array ( 3 downto 0 )
tob_xoff_assert_cnt_32b_B	in	mgt_data_array ( 3 downto 0 )
raw_xoff_assert_cnt_32b	in	mgt_data_array ( 3 downto 0 )
merged_xoff_assert_cnt_32b_A	in	mgt_data_array ( 1 downto 0 )
merged_xoff_assert_cnt_32b_B	in	mgt_data_array ( 1 downto 0 )

Detailed Description

Control FPGA data_path slave registers.

This module provides IPBus access for all Read Only and Read/Write registers within the Control FPGA data_path block.

Author

Saeed Taghavi and David Sankey

Definition at line 20 of file rdout_ipb_slave.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd