eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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rdout_ipb_slave.vhd
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1 
7 
8 library IEEE;
9 use IEEE.STD_LOGIC_1164.all;
10 use ieee.numeric_std.all;
11 
12 library ipbus_lib;
13 use ipbus_lib.ipbus.all;
14 
15 library infrastructure_lib;
16 use infrastructure_lib.packet_mux_type.all;
17 use infrastructure_lib.ipbus_decode_efex_cntrl_data_path.all; -- package
18 
20 entity rdout_ipb_slave is
21  generic (
22  TOB_FIFO_MAX_ADDR_WIDTH: positive := 12;
24  MERGED_FIFO_MAX_ADDR_WIDTH: positive := 11;
26  RAW_FIFO_MAX_ADDR_WIDTH: positive := 11;
28  PACKET_MAX_WIDTH: positive := 8
30  );
31  port (
32  clk_320 : in std_logic;
34  ipb_rst : in std_logic;
36  ipb_clk : in std_logic;
38  IPb_in : in ipb_wbus; -- The signals going from master to slaves
40  IPb_out : out ipb_rbus; -- The signals going from slaves to master
41 
43  ipbus_out_tob_mgt_wbus_array : out ipb_wbus_array(3 downto 0); -- array of wbus
44  ipbus_in_tob_mgt_rbus_array : in ipb_rbus_array(3 downto 0); -- array of rbus
46  ipbus_out_raw_mgt_wbus_array : out ipb_wbus_array(3 downto 0);
47  ipbus_in_raw_mgt_rbus_array : in ipb_rbus_array(3 downto 0);
49  ipbus_out_merger_spy_wbus_array : out ipb_wbus_array(1 downto 0);
50  ipbus_in_merger_spy_rbus_array : in ipb_rbus_array(1 downto 0);
52  ipbus_out_built_fifo_wbus_array : out ipb_wbus_array(1 downto 0);
53  ipbus_in_built_fifo_rbus_array : in ipb_rbus_array(1 downto 0);
54 
56  bcr_320 : in std_logic;
57  ecr_320 : in std_logic;
58  readout_delay : out std_logic_vector(31 downto 0);
59  counter_control : out std_logic_vector(31 downto 0);
60  spy_ram_rst_wr_addr : out std_logic_vector (31 downto 0);
61  wraparound_enable : out std_logic_vector(31 downto 0);
62 
64  tob_fifo_prog_full_thresh_assert : out std_logic_vector(15 downto 0);
65  tob_fifo_prog_full_thresh_negate : out std_logic_vector(15 downto 0);
66  raw_fifo_prog_full_thresh_assert : out std_logic_vector(15 downto 0);
67  raw_fifo_prog_full_thresh_negate : out std_logic_vector(15 downto 0);
68 
70  tob_fifo_XOFF_thresh_assert : out std_logic_vector(15 downto 0);
71  tob_fifo_XOFF_thresh_negate : out std_logic_vector(15 downto 0);
72  raw_fifo_XOFF_thresh_assert : out std_logic_vector(15 downto 0);
73  raw_fifo_XOFF_thresh_negate : out std_logic_vector(15 downto 0);
74  merged_fifo_XOFF_thresh_assert : out std_logic_vector(15 downto 0);
75  merged_fifo_XOFF_thresh_negate : out std_logic_vector(15 downto 0);
76  dbg_fifo_XOFF_thresh_assert : out std_logic_vector(15 downto 0);
77  dbg_fifo_XOFF_thresh_negate : out std_logic_vector(15 downto 0);
78 
79 -- MGT status blocks
80  tob_mgt_packet_received_cnt_bus : in mgt_data_array(3 downto 0);
81  tob_mgt_safe_mode_cnt_bus : in mgt_data_array(3 downto 0);
82  tob_mgt_packet_err_cnt_bus : in mgt_data_array(3 downto 0);
83  tob_mgt_length_err_cnt_bus : in mgt_data_array(3 downto 0);
84  tob_mgt_bcn_err_cnt_bus : in mgt_data_array(3 downto 0);
85  tob_mgt_last_l1id_bus : in mgt_data_array(3 downto 0);
86  tob_mgt_last_error_l1id_bus : in mgt_data_array(3 downto 0);
87  raw_mgt_packet_received_cnt_bus : in mgt_data_array(3 downto 0);
88  raw_mgt_safe_mode_cnt_bus : in mgt_data_array(3 downto 0);
89  raw_mgt_packet_err_cnt_bus : in mgt_data_array(3 downto 0);
90  raw_mgt_length_err_cnt_bus : in mgt_data_array(3 downto 0);
91  raw_mgt_last_l1id_bus : in mgt_data_array(3 downto 0);
92  raw_mgt_last_error_l1id_bus : in mgt_data_array(3 downto 0);
93 
94 -- TOB FIFO status blocks
95  tob_fifo_fill_level_A_bus : in fifo_status_array(3 downto 0); -- array of 16-bits
96  tob_packet_count_A_bus : in fifo_status_array(3 downto 0); -- array of 16-bits
97  tob_fifo_tide_mark_A_bus : in fifo_status_array(3 downto 0); -- array of 16-bits
98  tob_packet_tide_mark_A_bus : in fifo_status_array(3 downto 0); -- array of 16-bits
99  tob_fifo_err_cnt_A_bus : in mgt_data_array(3 downto 0); -- 32-bit error counter
100  tob_fifo_fill_level_B_bus : in fifo_status_array(3 downto 0);
101  tob_packet_count_B_bus : in fifo_status_array(3 downto 0);
102  tob_fifo_tide_mark_B_bus : in fifo_status_array(3 downto 0); -- array of 16-bits
103  tob_packet_tide_mark_B_bus : in fifo_status_array(3 downto 0); -- array of 16-bits
104  tob_fifo_err_cnt_B_bus : in mgt_data_array(3 downto 0); -- 32-bit error counter
105 
106 -- Merged FIFO status blocks
107  merged_fifo_fill_level_A_bus: in fifo_status_array(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1) 16-bits inputs
108  merged_packet_count_A_bus : in fifo_status_array(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1) 16-bits
109  merged_fifo_tide_mark_A_bus : in fifo_status_array(1 downto 0); -- array of 16-bits
110  merged_packet_tide_mark_A_bus : in fifo_status_array(1 downto 0); -- array of 16-bits
111  merged_fifo_err_cnt_A_bus : in mgt_data_array(1 downto 0); -- 16-bits; -- merged TOB FIFO (0), debug FIFO (1) count errors
112  merged_fifo_fill_level_B_bus: in fifo_status_array(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1)
113  merged_packet_count_B_bus : in fifo_status_array(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1)
114  merged_fifo_tide_mark_B_bus : in fifo_status_array(1 downto 0); -- array of 16-bits
115  merged_packet_tide_mark_B_bus : in fifo_status_array(1 downto 0); -- array of 16-bits
116  merged_fifo_err_cnt_B_bus : in mgt_data_array(1 downto 0); -- 32-bits; -- merged TOB FIFO (0), debug FIFO (1)
117 
118 -- Raw FIFO status block
119  raw_fifo_fill_level_bus : in fifo_status_array(3 downto 0); -- 16-bits
120  raw_packet_count_bus : in fifo_status_array(3 downto 0);
121  raw_fifo_tide_mark_bus : in fifo_status_array(3 downto 0); -- array of 16-bits
122  raw_packet_tide_mark_bus : in fifo_status_array(3 downto 0); -- array of 16-bits
123  raw_fifo_err_cnt_bus : in mgt_data_array(3 downto 0); -- 32-bit error counter
124 
125 -- Merger L1A status
126  L1A_cnt_merger_A : in std_logic_vector(31 downto 0);
127  L1A_cnt_merger_B : in std_logic_vector(31 downto 0);
128  Last_L1ID_merger_A : in std_logic_vector(31 downto 0); -- ECRID and L1ID
129  Last_L1ID_merger_B : in std_logic_vector(31 downto 0);
130 -- TOB merging counts per Processor FPGA
131  TOB_packet_merged_cnt_A_bus : in mgt_data_array(3 downto 0); -- array 4 of 32-bit counters
132  TOB_packet_missing_cnt_A_bus : in mgt_data_array(3 downto 0);
133  debug_packet_created_cnt_A_bus : in mgt_data_array(3 downto 0);
134  TOB_packet_merged_cnt_B_bus : in mgt_data_array(3 downto 0);
135  TOB_packet_missing_cnt_B_bus : in mgt_data_array(3 downto 0);
136  debug_packet_created_cnt_B_bus : in mgt_data_array(3 downto 0);
137 
138 -- MUX status blocks
139  mux_orbit_active_bus : in fifo_status_array(1 downto 0);
140  mux_orbit_active_tide_mark_bus : in fifo_status_array(1 downto 0);
141  mux_a_active_bus : in fifo_status_array(5 downto 0);
142  mux_b_active_bus : in fifo_status_array(5 downto 0);
143  mux_a_active_tide_mark_bus : in fifo_status_array(5 downto 0);
144  mux_b_active_tide_mark_bus : in fifo_status_array(5 downto 0);
145  mux_a_pkt_cnt_bus : in mgt_data_array(5 downto 0);
146  mux_b_pkt_cnt_bus : in mgt_data_array(5 downto 0);
147  mux_a_last_l1id_bus : in mgt_data_array(5 downto 0);
148  mux_b_last_l1id_bus : in mgt_data_array(5 downto 0);
149 
150 -- BUSY and XOff counters
151  fifo_bc_count : in std_logic_vector(31 downto 0);
152  tob_busy_cnt_32b_A : in mgt_data_array(3 downto 0); -- 32-bits
153  tob_busy_cnt_32b_B : in mgt_data_array(3 downto 0); -- 32-bits
154  raw_busy_cnt_32b : in mgt_data_array(3 downto 0); -- 32-bits
155 
156  tob_busy_active_cnt_32b_A : in mgt_data_array(3 downto 0); -- 32-bits
157  tob_busy_active_cnt_32b_B : in mgt_data_array(3 downto 0); -- 32-bits
158  raw_busy_active_cnt_32b : in mgt_data_array(3 downto 0); -- 32-bits
159 
160  tob_busy_assert_cnt_32b_A : in mgt_data_array(3 downto 0); -- 32-bits
161  tob_busy_assert_cnt_32b_B : in mgt_data_array(3 downto 0); -- 32-bits
162  raw_busy_assert_cnt_32b : in mgt_data_array(3 downto 0); -- 32-bits
163 
164  tob_xoff_cnt_32b_A : in mgt_data_array(3 downto 0); -- 32-bits
165  tob_xoff_cnt_32b_B : in mgt_data_array(3 downto 0); -- 32-bits
166  raw_xoff_cnt_32b : in mgt_data_array(3 downto 0); -- 32-bits
167  merged_xoff_cnt_32b_A : in mgt_data_array(1 downto 0); -- 32-bits
168  merged_xoff_cnt_32b_B : in mgt_data_array(1 downto 0); -- 32-bits
169 
170  tob_xoff_active_cnt_32b_A : in mgt_data_array(3 downto 0); -- 32-bits
171  tob_xoff_active_cnt_32b_B : in mgt_data_array(3 downto 0); -- 32-bits
172  raw_xoff_active_cnt_32b : in mgt_data_array(3 downto 0); -- 32-bits
173  merged_xoff_active_cnt_32b_A: in mgt_data_array(1 downto 0); -- 32-bits
174  merged_xoff_active_cnt_32b_B: in mgt_data_array(1 downto 0); -- 32-bits
175 
176  tob_xoff_assert_cnt_32b_A : in mgt_data_array(3 downto 0); -- 32-bits
177  tob_xoff_assert_cnt_32b_B : in mgt_data_array(3 downto 0); -- 32-bits
178  raw_xoff_assert_cnt_32b : in mgt_data_array(3 downto 0); -- 32-bits
179  merged_xoff_assert_cnt_32b_A: in mgt_data_array(1 downto 0); -- 32-bits
180  merged_xoff_assert_cnt_32b_B: in mgt_data_array(1 downto 0) -- 32-bits
181  );
182 end rdout_ipb_slave;
183 
185 architecture Behavioral of rdout_ipb_slave is
186  type integer_array is array(natural range <>) of integer range 0 to N_SLAVES;
187 -- fifo_status_array is array(natural range <>) of std_logic_vector(15 downto 0)
188 -- mgt_data_array is array(natural range <>) of std_logic_vector(31 downto 0)
189  signal ipbw : ipb_wbus_array(N_SLAVES - 1 downto 0);
190  signal ipbr : ipb_rbus_array(N_SLAVES - 1 downto 0);
191 
192  signal update_counter_reg_i : std_logic_vector(31 downto 0);
193  signal update_counter_reg_1, update_counter_reg_2, update_counter_reg_3, update_counter_bcr, update_counter_reg : std_logic;
194 
195  signal tob_fifo_prog_full_thresh_assert_i, tob_fifo_prog_full_thresh_negate_i, raw_fifo_prog_full_thresh_assert_i, raw_fifo_prog_full_thresh_negate_i: std_logic_vector(31 downto 0);
196  signal tob_fifo_xoff_thresh_assert_i, tob_fifo_xoff_thresh_negate_i, merged_fifo_xoff_thresh_assert_i, merged_fifo_xoff_thresh_negate_i: std_logic_vector(31 downto 0);
197  signal raw_fifo_xoff_thresh_assert_i, raw_fifo_xoff_thresh_negate_i, dbg_fifo_xoff_thresh_assert_i, dbg_fifo_xoff_thresh_negate_i: std_logic_vector(31 downto 0);
198 --
199  signal mgt_packet_count_bus, mgt_safe_mode_count_bus, mgt_mgt_error_count_bus, mgt_length_error_count_bus, mgt_bcn_error_count_bus, mgt_last_l1id_bus, mgt_bad_l1id_bus: mgt_data_array(7 downto 0);
200  signal fifo_fill_level_bus, fifo_fill_level_watermark_bus, fifo_packet_count_bus, fifo_packet_count_watermark_bus: fifo_status_array(15 downto 0);
201  signal fifo_bc_count_i: std_logic_vector(31 downto 0);
202  signal fifo_xoff_total_count_bus, fifo_xoff_last_count_bus, fifo_xoff_assert_count_bus, fifo_busy_total_count_bus, fifo_busy_last_count_bus, fifo_busy_assert_count_bus, fifo_error_count_bus: mgt_data_array(15 downto 0);
203  signal merger_l1a_count_bus, merger_last_l1id_bus: mgt_data_array(1 downto 0);
204  signal merger_merged_count_bus, merger_missing_count_bus, merger_debug_count_bus: mgt_data_array(7 downto 0);
205  signal mux_orbit_active_bus_i, mux_orbit_active_watermark_bus: fifo_status_array(1 downto 0);
206  signal mux_packet_active_bus, mux_packet_active_watermark_bus: fifo_status_array(11 downto 0);
207  signal mux_packet_count_bus, mux_last_l1id_bus: mgt_data_array(11 downto 0);
208 -- Mapping onto IPBus slave buses
209  constant mgt_slv_bus: integer_array(7 downto 0) := (
210  N_SLV_RAW_MGT_STATUS_P3, N_SLV_RAW_MGT_STATUS_P2, N_SLV_RAW_MGT_STATUS_P1, N_SLV_RAW_MGT_STATUS_P0,
211  N_SLV_TOB_MGT_STATUS_P3, N_SLV_TOB_MGT_STATUS_P2, N_SLV_TOB_MGT_STATUS_P1, N_SLV_TOB_MGT_STATUS_P0);
212  constant fifo_slv_bus: integer_array(15 downto 0) := (
213  N_SLV_MERGED_FIFO_STATUS_B_DEBUG, N_SLV_MERGED_FIFO_STATUS_B_TOB, N_SLV_MERGED_FIFO_STATUS_A_DEBUG, N_SLV_MERGED_FIFO_STATUS_A_TOB,
214  N_SLV_RAW_FIFO_STATUS_P3, N_SLV_RAW_FIFO_STATUS_P2, N_SLV_RAW_FIFO_STATUS_P1, N_SLV_RAW_FIFO_STATUS_P0,
215  N_SLV_TOB_FIFO_STATUS_B_P3, N_SLV_TOB_FIFO_STATUS_B_P2, N_SLV_TOB_FIFO_STATUS_B_P1, N_SLV_TOB_FIFO_STATUS_B_P0,
216  N_SLV_TOB_FIFO_STATUS_A_P3, N_SLV_TOB_FIFO_STATUS_A_P2, N_SLV_TOB_FIFO_STATUS_A_P1, N_SLV_TOB_FIFO_STATUS_A_P0);
217  constant merger_status_slv_bus: integer_array(1 downto 0) := (N_SLV_TOB_MERGER_STATUS_B_MERGER, N_SLV_TOB_MERGER_STATUS_A_MERGER);
218  constant merger_slv_bus: integer_array(7 downto 0) := (
219  N_SLV_TOB_MERGER_STATUS_B_P3, N_SLV_TOB_MERGER_STATUS_B_P2, N_SLV_TOB_MERGER_STATUS_B_P1, N_SLV_TOB_MERGER_STATUS_B_P0,
220  N_SLV_TOB_MERGER_STATUS_A_P3, N_SLV_TOB_MERGER_STATUS_A_P2, N_SLV_TOB_MERGER_STATUS_A_P1, N_SLV_TOB_MERGER_STATUS_A_P0);
221  constant mux_active_slv_bus: integer_array(1 downto 0) := (N_SLV_MUX_STATUS_B_MUX_ACTIVE, N_SLV_MUX_STATUS_A_MUX_ACTIVE);
222  constant mux_slv_bus: integer_array(11 downto 0) := (
223  N_SLV_MUX_STATUS_B_RAW_3, N_SLV_MUX_STATUS_B_RAW_2, N_SLV_MUX_STATUS_B_RAW_1, N_SLV_MUX_STATUS_B_RAW_0, N_SLV_MUX_STATUS_B_DEBUG, N_SLV_MUX_STATUS_B_TOB,
224  N_SLV_MUX_STATUS_A_RAW_3, N_SLV_MUX_STATUS_A_RAW_2, N_SLV_MUX_STATUS_A_RAW_1, N_SLV_MUX_STATUS_A_RAW_0, N_SLV_MUX_STATUS_A_DEBUG, N_SLV_MUX_STATUS_A_TOB);
225 
226 -- Allow for two events headroom in TOB FIFO to account for latency through merging block and four times the size in merged FIFO to account for merging itself!
227  constant tob_fifo_default_busy_assert_threshold : std_logic_vector(31 downto 0) := (31 downto TOB_FIFO_MAX_ADDR_WIDTH => '0') & (TOB_FIFO_MAX_ADDR_WIDTH-1 downto PACKET_MAX_WIDTH => '1') & (PACKET_MAX_WIDTH-1 downto 0 => '0');
228  constant tob_fifo_default_busy_negate_threshold : std_logic_vector(31 downto 0) := (31 downto TOB_FIFO_MAX_ADDR_WIDTH => '0') & (TOB_FIFO_MAX_ADDR_WIDTH-1 downto PACKET_MAX_WIDTH+1 => '1') & (PACKET_MAX_WIDTH downto 0 => '0');
229  constant raw_fifo_default_busy_assert_threshold : std_logic_vector(31 downto 0) := (31 downto RAW_FIFO_MAX_ADDR_WIDTH => '0') & (RAW_FIFO_MAX_ADDR_WIDTH-1 downto PACKET_MAX_WIDTH-1 => '1') & (PACKET_MAX_WIDTH-2 downto 0 => '0');
230  constant raw_fifo_default_busy_negate_threshold : std_logic_vector(31 downto 0) := (31 downto RAW_FIFO_MAX_ADDR_WIDTH => '0') & (RAW_FIFO_MAX_ADDR_WIDTH-1 downto PACKET_MAX_WIDTH => '1') & (PACKET_MAX_WIDTH-1 downto 0 => '0');
231  constant tob_fifo_default_assert_threshold : std_logic_vector(31 downto 0) := (31 downto TOB_FIFO_MAX_ADDR_WIDTH => '0') & (TOB_FIFO_MAX_ADDR_WIDTH-1 downto PACKET_MAX_WIDTH+1 => '1') & (PACKET_MAX_WIDTH downto 0 => '0');
232  constant tob_fifo_default_negate_threshold : std_logic_vector(31 downto 0) := (31 downto TOB_FIFO_MAX_ADDR_WIDTH => '0') & (TOB_FIFO_MAX_ADDR_WIDTH-1 downto PACKET_MAX_WIDTH+2 => '1') & (PACKET_MAX_WIDTH+1 downto 0 => '0');
233  constant merged_fifo_default_assert_threshold : std_logic_vector(31 downto 0) := (31 downto MERGED_FIFO_MAX_ADDR_WIDTH => '0') & (MERGED_FIFO_MAX_ADDR_WIDTH-1 downto PACKET_MAX_WIDTH+2 => '1') & (PACKET_MAX_WIDTH+1 downto 0 => '0');
234  constant merged_fifo_default_negate_threshold : std_logic_vector(31 downto 0) := (31 downto MERGED_FIFO_MAX_ADDR_WIDTH => '0') & (MERGED_FIFO_MAX_ADDR_WIDTH-1 downto PACKET_MAX_WIDTH+3 => '1') & (PACKET_MAX_WIDTH+2 downto 0 => '0');
235  constant raw_fifo_default_assert_threshold : std_logic_vector(31 downto 0) := (31 downto RAW_FIFO_MAX_ADDR_WIDTH => '0') & (RAW_FIFO_MAX_ADDR_WIDTH-1 downto PACKET_MAX_WIDTH => '1') & (PACKET_MAX_WIDTH-1 downto 0 => '0');
236  constant raw_fifo_default_negate_threshold : std_logic_vector(31 downto 0) := (31 downto RAW_FIFO_MAX_ADDR_WIDTH => '0') & (RAW_FIFO_MAX_ADDR_WIDTH-1 downto PACKET_MAX_WIDTH+1 => '1') & (PACKET_MAX_WIDTH downto 0 => '0');
237 
238 begin
239 
240 ---- access to tob_mgt DPRAM spy memeory
241  ipbus_out_tob_mgt_wbus_array(0) <= ipbw(N_SLV_TOB_MGT_P0_SPY_RAM); -- signal going to SPY DPRAM
242  ipbr(N_SLV_TOB_MGT_P0_SPY_RAM) <= ipbus_in_tob_mgt_rbus_array(0); -- signal coming from SPY DPRAM
243  ipbus_out_tob_mgt_wbus_array(1) <= ipbw(N_SLV_TOB_MGT_P1_SPY_RAM); -- signal going to SPY DPRAM
244  ipbr(N_SLV_TOB_MGT_P1_SPY_RAM) <= ipbus_in_tob_mgt_rbus_array(1); -- signal coming from SPY DPRAM
245  ipbus_out_tob_mgt_wbus_array(2) <= ipbw(N_SLV_TOB_MGT_P2_SPY_RAM); -- signal going to SPY DPRAM
246  ipbr(N_SLV_TOB_MGT_P2_SPY_RAM) <= ipbus_in_tob_mgt_rbus_array(2); -- signal coming from SPY DPRAM
247  ipbus_out_tob_mgt_wbus_array(3) <= ipbw(N_SLV_TOB_MGT_P3_SPY_RAM); -- signal going to SPY DPRAM
248  ipbr(N_SLV_TOB_MGT_P3_SPY_RAM) <= ipbus_in_tob_mgt_rbus_array(3); -- signal coming from SPY DPRAM
249 
250 ---- access to raw_mgt DPRAM spy memeory
251  ipbus_out_raw_mgt_wbus_array(0) <= ipbw(N_SLV_RAW_MGT_P0_SPY_RAM); -- signal going to SPY DPRAM
252  ipbr(N_SLV_RAW_MGT_P0_SPY_RAM) <= ipbus_in_raw_mgt_rbus_array(0); -- signal coming from SPY DPRAM
253  ipbus_out_raw_mgt_wbus_array(1) <= ipbw(N_SLV_RAW_MGT_P1_SPY_RAM); -- signal going to SPY DPRAM
254  ipbr(N_SLV_RAW_MGT_P1_SPY_RAM) <= ipbus_in_raw_mgt_rbus_array(1); -- signal coming from SPY DPRAM
255  ipbus_out_raw_mgt_wbus_array(2) <= ipbw(N_SLV_RAW_MGT_P2_SPY_RAM); -- signal going to SPY DPRAM
256  ipbr(N_SLV_RAW_MGT_P2_SPY_RAM) <= ipbus_in_raw_mgt_rbus_array(2); -- signal coming from SPY DPRAM
257  ipbus_out_raw_mgt_wbus_array(3) <= ipbw(N_SLV_RAW_MGT_P3_SPY_RAM); -- signal going to SPY DPRAM
258  ipbr(N_SLV_RAW_MGT_P3_SPY_RAM) <= ipbus_in_raw_mgt_rbus_array(3); -- signal coming from SPY DPRAM
259 
260 ---- access to Merger debug DPRAM spy memeory
261  ipbus_out_merger_spy_wbus_array(0) <= ipbw(N_SLV_TOB_MERGER_A_DEBUG_SPY_RAM); -- signal going to SPY DPRAM
262  ipbr(N_SLV_TOB_MERGER_A_DEBUG_SPY_RAM) <= ipbus_in_merger_spy_rbus_array(0); -- signal coming from SPY DPRAM
263  ipbus_out_merger_spy_wbus_array(1) <= ipbw(N_SLV_TOB_MERGER_B_DEBUG_SPY_RAM); -- signal going to SPY DPRAM
264  ipbr(N_SLV_TOB_MERGER_B_DEBUG_SPY_RAM) <= ipbus_in_merger_spy_rbus_array(1); -- signal coming from SPY DPRAM
265 
266 ---- access to aurora_channel DPRAM spy memeory
267  ipbus_out_built_fifo_wbus_array(0) <= ipbw(N_SLV_AURORA_CHANNEL0_SPY_RAM); -- signal going to SPY DPRAM
268  ipbr(N_SLV_AURORA_CHANNEL0_SPY_RAM) <= ipbus_in_built_fifo_rbus_array(0); -- signal coming from SPY DPRAM
269  ipbus_out_built_fifo_wbus_array(1) <= ipbw(N_SLV_AURORA_CHANNEL1_SPY_RAM); -- signal going to SPY DPRAM
270  ipbr(N_SLV_AURORA_CHANNEL1_SPY_RAM) <= ipbus_in_built_fifo_rbus_array(1); -- signal coming from SPY DPRAM
271 
272 -- only use 16-b out of the 32-b registers...
273  tob_fifo_prog_full_thresh_assert <= tob_fifo_prog_full_thresh_assert_i(15 downto 0);
274  tob_fifo_prog_full_thresh_negate <= tob_fifo_prog_full_thresh_negate_i(15 downto 0);
275  raw_fifo_prog_full_thresh_assert <= raw_fifo_prog_full_thresh_assert_i(15 downto 0);
276  raw_fifo_prog_full_thresh_negate <= raw_fifo_prog_full_thresh_negate_i(15 downto 0);
277 
278  tob_fifo_xoff_thresh_assert <= tob_fifo_xoff_thresh_assert_i(15 downto 0);
279  tob_fifo_xoff_thresh_negate <= tob_fifo_xoff_thresh_negate_i(15 downto 0);
280  merged_fifo_xoff_thresh_assert <= merged_fifo_xoff_thresh_assert_i(15 downto 0);
281  merged_fifo_xoff_thresh_negate <= merged_fifo_xoff_thresh_negate_i(15 downto 0);
282  raw_fifo_xoff_thresh_assert <= raw_fifo_xoff_thresh_assert_i(15 downto 0);
283  raw_fifo_xoff_thresh_negate <= raw_fifo_xoff_thresh_negate_i(15 downto 0);
284  dbg_fifo_xoff_thresh_assert <= dbg_fifo_xoff_thresh_assert_i(15 downto 0);
285  dbg_fifo_xoff_thresh_negate <= dbg_fifo_xoff_thresh_negate_i(15 downto 0);
286 
287  counter_control <= update_counter_reg_i;
288 
289 ipbus_fabric: entity ipbus_lib.ipbus_fabric_sel
290  generic map(NSLV => N_SLAVES, SEL_WIDTH => IPBUS_SEL_WIDTH)
291  port map(
292  ipb_in => ipb_in,
293  ipb_out => ipb_out,
294  sel => ipbus_sel_efex_cntrl_data_path(ipb_in.ipb_addr),
295  ipb_to_slaves => ipbw,
296  ipb_from_slaves => ipbr
297  );
298 
299 control_registers: entity ipbus_lib.ipbus_ctrlreg_v
300  generic map(N_CTRL => 4, N_STAT => 1)
301  port map(
302  clk => ipb_clk,
303  reset => ipb_rst,
304  ipbus_in => ipbw(N_SLV_CONTROL),
305  ipbus_out => ipbr(N_SLV_CONTROL),
306  q(0) => readout_delay,
307  q(1) => update_counter_reg_i, -- read/write reg
308  q(2) => spy_ram_rst_wr_addr, -- read/write reg
309  q(3) => wraparound_enable, -- read/write reg
310  ctrl_default(0) => x"00000507", -- 5*4 BC IFG and 7*32 BC delay before packet building
311  ctrl_default(1) => x"002bd702", -- update at about 1 Hz
312  ctrl_default(2) => (Others => '0'),
313  ctrl_default(3) => (Others => '0'),
314  d(0) => fifo_bc_count_i,
315  stb => open);
316 
317 update_counter_bcr_block: process(clk_320)
318 variable bcr_counter, bcr_match: unsigned(23 downto 0) := (Others => '0');
319 begin
320  if rising_edge(clk_320) then
321  bcr_match := unsigned(update_counter_reg_i(31 downto 8));
322  if (ecr_320 = '1') then
323  update_counter_bcr <= '0';
324  bcr_counter := (Others => '0');
325  elsif (bcr_320 = '1') then
326  if (bcr_counter >= bcr_match) then
327  update_counter_bcr <= update_counter_reg_i(1);
328  bcr_counter := (Others => '0');
329  else
330  update_counter_bcr <= '0';
331  bcr_counter := bcr_counter + 1;
332  end if;
333  else
334  update_counter_bcr <= '0';
335  end if;
336  end if;
337 end process update_counter_bcr_block;
338 
339 register_update_control: process(clk_320)
340 begin
341  if rising_edge(clk_320) then
342  update_counter_reg_1 <= update_counter_reg_i(0);
343  update_counter_reg_2 <= update_counter_reg_1;
344  update_counter_reg_3 <= update_counter_reg_i(2);
345  if (update_counter_reg_1 = '1' and update_counter_reg_2 = '0') or (update_counter_reg_3 = '1') or (update_counter_bcr = '1') then
346  update_counter_reg <= '1';
347  else
348  update_counter_reg <= '0';
349  end if;
350  end if;
351 end process register_update_control;
352 
353 register_update: process(clk_320)
354 begin
355  if rising_edge(clk_320) then
356  if update_counter_reg = '1' then
357 -- MGT status buses
358  mgt_packet_count_bus <= raw_mgt_packet_received_cnt_bus & tob_mgt_packet_received_cnt_bus;
359  mgt_safe_mode_count_bus <= raw_mgt_safe_mode_cnt_bus & tob_mgt_safe_mode_cnt_bus;
360  mgt_mgt_error_count_bus <= raw_mgt_packet_err_cnt_bus & tob_mgt_packet_err_cnt_bus;
361  mgt_length_error_count_bus <= raw_mgt_length_err_cnt_bus & tob_mgt_length_err_cnt_bus;
362  mgt_bcn_error_count_bus(3 downto 0) <= tob_mgt_bcn_err_cnt_bus;
363  mgt_bcn_error_count_bus(7 downto 4) <= (Others => (Others => '0'));
364  mgt_last_l1id_bus <= raw_mgt_last_l1id_bus & tob_mgt_last_l1id_bus;
365  mgt_bad_l1id_bus <= raw_mgt_last_error_l1id_bus & tob_mgt_last_error_l1id_bus;
366 -- FIFO status buses
367  fifo_fill_level_bus <= merged_fifo_fill_level_B_bus & merged_fifo_fill_level_A_bus & raw_fifo_fill_level_bus & tob_fifo_fill_level_B_bus & tob_fifo_fill_level_A_bus;
368  fifo_fill_level_watermark_bus <= merged_fifo_tide_mark_B_bus & merged_fifo_tide_mark_A_bus & raw_fifo_tide_mark_bus & tob_fifo_tide_mark_B_bus & tob_fifo_tide_mark_A_bus;
369  fifo_packet_count_bus <= merged_packet_count_B_bus & merged_packet_count_A_bus & raw_packet_count_bus & tob_packet_count_B_bus & tob_packet_count_A_bus;
370  fifo_packet_count_watermark_bus <= merged_packet_tide_mark_B_bus & merged_packet_tide_mark_A_bus & raw_packet_tide_mark_bus & tob_packet_tide_mark_B_bus & tob_packet_tide_mark_A_bus;
371  fifo_xoff_total_count_bus <= merged_xoff_cnt_32b_B & merged_xoff_cnt_32b_A & raw_xoff_cnt_32b & tob_xoff_cnt_32b_B & tob_xoff_cnt_32b_A;
372  fifo_xoff_last_count_bus <= merged_xoff_active_cnt_32b_B & merged_xoff_active_cnt_32b_A & raw_xoff_active_cnt_32b & tob_xoff_active_cnt_32b_B & tob_xoff_active_cnt_32b_A;
373  fifo_xoff_assert_count_bus <= merged_xoff_assert_cnt_32b_B & merged_xoff_assert_cnt_32b_A & raw_xoff_assert_cnt_32b & tob_xoff_assert_cnt_32b_B & tob_xoff_assert_cnt_32b_A;
374  fifo_busy_total_count_bus(15 downto 12) <= (Others => (Others => '0')); -- no BUSY from merger FIFOs...
375  fifo_busy_total_count_bus(11 downto 0) <= raw_busy_cnt_32b & tob_busy_cnt_32b_B & tob_busy_cnt_32b_A;
376  fifo_busy_last_count_bus(15 downto 12) <= (Others => (Others => '0')); -- no BUSY from merger FIFOs...
377  fifo_busy_last_count_bus(11 downto 0) <= raw_busy_active_cnt_32b & tob_busy_active_cnt_32b_B & tob_busy_active_cnt_32b_A;
378  fifo_busy_assert_count_bus(15 downto 12) <= (Others => (Others => '0')); -- no BUSY from merger FIFOs...
379  fifo_busy_assert_count_bus(11 downto 0) <= raw_busy_assert_cnt_32b & tob_busy_assert_cnt_32b_B & tob_busy_assert_cnt_32b_A;
380  fifo_error_count_bus <= merged_fifo_err_cnt_B_bus & merged_fifo_err_cnt_A_bus & raw_fifo_err_cnt_bus & tob_fifo_err_cnt_B_bus & tob_fifo_err_cnt_A_bus;
381 -- Merger status buses
382  merger_l1a_count_bus <= L1A_cnt_merger_B & L1A_cnt_merger_A;
383  merger_last_l1id_bus <= Last_L1ID_merger_B & Last_L1ID_merger_A;
384  merger_merged_count_bus <= TOB_packet_merged_cnt_B_bus & TOB_packet_merged_cnt_A_bus;
385  merger_missing_count_bus <= TOB_packet_missing_cnt_B_bus & TOB_packet_missing_cnt_A_bus;
386  merger_debug_count_bus <= debug_packet_created_cnt_B_bus & debug_packet_created_cnt_A_bus;
387 -- MUX status buses
388  fifo_bc_count_i <= fifo_bc_count;
389  mux_orbit_active_bus_i <= mux_orbit_active_bus;
390  mux_orbit_active_watermark_bus <= mux_orbit_active_tide_mark_bus;
391  mux_packet_active_bus <= mux_b_active_bus & mux_a_active_bus;
392  mux_packet_active_watermark_bus <= mux_b_active_tide_mark_bus & mux_a_active_tide_mark_bus;
393  mux_packet_count_bus <= mux_b_pkt_cnt_bus & mux_a_pkt_cnt_bus;
394  mux_last_l1id_bus <= mux_b_last_l1id_bus & mux_a_last_l1id_bus;
395  end if;
396  end if;
397 end process register_update;
398 
399 mgt_status_generate_block: for i in 0 to 7 generate
400  mgt_status: entity ipbus_lib.ipbus_ctrlreg_v
401  generic map(N_CTRL => 0, N_STAT => 7)
402  port map(
403  clk => ipb_clk,
404  reset => ipb_rst,
405  ipbus_in => ipbw(mgt_slv_bus(i)),
406  ipbus_out => ipbr(mgt_slv_bus(i)),
407  d(0) => mgt_packet_count_bus(i),
408  d(1) => mgt_safe_mode_count_bus(i),
409  d(2) => mgt_mgt_error_count_bus(i),
410  d(3) => mgt_length_error_count_bus(i),
411  d(4) => mgt_bcn_error_count_bus(i),
412  d(5) => mgt_last_l1id_bus(i),
413  d(6) => mgt_bad_l1id_bus(i),
414  q => open, -- read/write reg
415  stb => open);
416 end generate mgt_status_generate_block;
417 
418 fifo_status_generate_block: for i in 0 to 15 generate
419  fifo_status: entity ipbus_lib.ipbus_ctrlreg_v
420  generic map(N_CTRL => 0, N_STAT => 9)
421  port map(
422  clk => ipb_clk,
423  reset => ipb_rst,
424  ipbus_in => ipbw(fifo_slv_bus(i)),
425  ipbus_out => ipbr(fifo_slv_bus(i)),
426  d(0)(31 downto 16) => fifo_fill_level_watermark_bus(i),
427  d(0)(15 downto 0) => fifo_fill_level_bus(i),
428  d(1)(31 downto 16) => fifo_packet_count_watermark_bus(i),
429  d(1)(15 downto 0) => fifo_packet_count_bus(i),
430  d(2) => fifo_xoff_total_count_bus(i),
431  d(3) => fifo_xoff_last_count_bus(i),
432  d(4) => fifo_xoff_assert_count_bus(i),
433  d(5) => fifo_busy_total_count_bus(i),
434  d(6) => fifo_busy_last_count_bus(i),
435  d(7) => fifo_busy_assert_count_bus(i),
436  d(8) => fifo_error_count_bus(i),
437  q => open, -- read/write reg
438  stb => open);
439 end generate fifo_status_generate_block;
440 
441 merger_overall_status_generate_block: for i in 0 to 1 generate
442  merger_overall_status: entity ipbus_lib.ipbus_ctrlreg_v
443  generic map(N_CTRL => 0, N_STAT => 2)
444  port map(
445  clk => ipb_clk,
446  reset => ipb_rst,
447  ipbus_in => ipbw(merger_status_slv_bus(i)),
448  ipbus_out => ipbr(merger_status_slv_bus(i)),
449  d(0) => merger_l1a_count_bus(i),
450  d(1) => merger_last_l1id_bus(i),
451  q => open, -- read/write reg
452  stb => open);
453 end generate merger_overall_status_generate_block;
454 
455 merger_channel_status_generate_block: for i in 0 to 7 generate
456  merger_channel_status: entity ipbus_lib.ipbus_ctrlreg_v
457  generic map(N_CTRL => 0, N_STAT => 3)
458  port map(
459  clk => ipb_clk,
460  reset => ipb_rst,
461  ipbus_in => ipbw(merger_slv_bus(i)),
462  ipbus_out => ipbr(merger_slv_bus(i)),
463  d(0) => merger_merged_count_bus(i),
464  d(1) => merger_missing_count_bus(i),
465  d(2) => merger_debug_count_bus(i),
466  q => open, -- read/write reg
467  stb => open);
468 end generate merger_channel_status_generate_block;
469 
470 mux_orbit_status_generate_block: for i in 0 to 1 generate
471  mux_orbit_status: entity ipbus_lib.ipbus_ctrlreg_v
472  generic map(N_CTRL => 0, N_STAT => 1)
473  port map(
474  clk => ipb_clk,
475  reset => ipb_rst,
476  ipbus_in => ipbw(mux_active_slv_bus(i)),
477  ipbus_out => ipbr(mux_active_slv_bus(i)),
478  d(0)(31 downto 16) => mux_orbit_active_watermark_bus(i),
479  d(0)(15 downto 0) => mux_orbit_active_bus_i(i),
480  q => open, -- read/write reg
481  stb => open);
482 end generate mux_orbit_status_generate_block;
483 
484 mux_channel_status_generate_block: for i in 0 to 11 generate
485  mux_channel_status: entity ipbus_lib.ipbus_ctrlreg_v
486  generic map(N_CTRL => 0, N_STAT => 3)
487  port map(
488  clk => ipb_clk,
489  reset => ipb_rst,
490  ipbus_in => ipbw(mux_slv_bus(i)),
491  ipbus_out => ipbr(mux_slv_bus(i)),
492  d(0)(31 downto 16) => mux_packet_active_watermark_bus(i),
493  d(0)(15 downto 0) => mux_packet_active_bus(i),
494  d(1) => mux_packet_count_bus(i),
495  d(2) => mux_last_l1id_bus(i),
496  q => open, -- read/write reg
497  stb => open);
498 end generate mux_channel_status_generate_block;
499 
500 fifo_control : entity ipbus_lib.ipbus_ctrlreg_v
501  generic map(N_CTRL => 12, N_STAT => 0)
502  port map(
503  clk => ipb_clk,
504  reset => ipb_rst,
505  ipbus_in => ipbw(N_SLV_FIFO_CONTROL),
506  ipbus_out => ipbr(N_SLV_FIFO_CONTROL),
507  d => (others => (others => '0')),
508  q(0) => tob_fifo_prog_full_thresh_assert_i, -- read/write reg
509  q(1) => tob_fifo_prog_full_thresh_negate_i, -- read/write reg
510  q(2) => raw_fifo_prog_full_thresh_assert_i, -- read/write reg
511  q(3) => raw_fifo_prog_full_thresh_negate_i, -- read/write reg
512  q(4) => tob_fifo_xoff_thresh_assert_i, -- read/write reg
513  q(5) => tob_fifo_xoff_thresh_negate_i, -- read/write reg
514  q(6) => raw_fifo_xoff_thresh_assert_i, -- read/write reg
515  q(7) => raw_fifo_xoff_thresh_negate_i, -- read/write reg
516  q(8) => merged_fifo_xoff_thresh_assert_i, -- read/write reg
517  q(9) => merged_fifo_xoff_thresh_negate_i, -- read/write reg
518  q(10) => dbg_fifo_xoff_thresh_assert_i, -- read/write reg
519  q(11) => dbg_fifo_xoff_thresh_negate_i, -- read/write reg
520  ctrl_default(0) => tob_fifo_default_busy_assert_threshold,
521  ctrl_default(1) => tob_fifo_default_busy_negate_threshold,
522  ctrl_default(2) => raw_fifo_default_busy_assert_threshold,
523  ctrl_default(3) => raw_fifo_default_busy_negate_threshold,
524  ctrl_default(4) => tob_fifo_default_assert_threshold,
525  ctrl_default(5) => tob_fifo_default_negate_threshold,
526  ctrl_default(6) => raw_fifo_default_assert_threshold,
527  ctrl_default(7) => raw_fifo_default_negate_threshold,
528  ctrl_default(8) => merged_fifo_default_assert_threshold,
529  ctrl_default(9) => merged_fifo_default_negate_threshold,
530  ctrl_default(10) => merged_fifo_default_assert_threshold,
531  ctrl_default(11) => merged_fifo_default_negate_threshold,
532  stb => open);
533 
534 end Behavioral;
ipbus_decode_efex_cntrl_data_path
Definition: ipbus_decode_efex_cntrl_data_path.vhd:15
packet_mux_type
Definition: packet_mux_type.vhd:4
rdout_ipb_slave.Behavioral
Control FPGA data_path slave registers.
Definition: rdout_ipb_slave.vhd:185
rdout_ipb_slave
Control FPGA data_path slave registers.
Definition: rdout_ipb_slave.vhd:20
rdout_ipb_slave.bcr_320
in bcr_320 std_logic
Control registers.
Definition: rdout_ipb_slave.vhd:56
rdout_ipb_slave.ipb_rst
in ipb_rst std_logic
IPBus Reset input.
Definition: rdout_ipb_slave.vhd:34
rdout_ipb_slave.MERGED_FIFO_MAX_ADDR_WIDTH
MERGED_FIFO_MAX_ADDR_WIDTH positive := 11
address bus width of TOB FIFO RAM in packet_fifo_block for each Processor FPGA
Definition: rdout_ipb_slave.vhd:24
rdout_ipb_slave.ipbus_out_raw_mgt_wbus_array
out ipbus_out_raw_mgt_wbus_array ipb_wbus_array( 3 downto 0)
MGT raw input spy RAMs.
Definition: rdout_ipb_slave.vhd:46
rdout_ipb_slave.IPb_out
out IPb_out ipb_rbus
IPBus output bus going from slaves to master.
Definition: rdout_ipb_slave.vhd:40
rdout_ipb_slave.ipbus_out_tob_mgt_wbus_array
out ipbus_out_tob_mgt_wbus_array ipb_wbus_array( 3 downto 0)
MGT TOB input spy RAMs.
Definition: rdout_ipb_slave.vhd:43
rdout_ipb_slave.ipbus_out_merger_spy_wbus_array
out ipbus_out_merger_spy_wbus_array ipb_wbus_array( 1 downto 0)
Merger debug spy RAMs.
Definition: rdout_ipb_slave.vhd:49
rdout_ipb_slave.IPb_in
in IPb_in ipb_wbus
IPBus input bus going from master to slaves.
Definition: rdout_ipb_slave.vhd:38
rdout_ipb_slave.PACKET_MAX_WIDTH
PACKET_MAX_WIDTH positive := 8
address bus width of RAW FIFO RAM in packet_fifo_block for each Processor FPGA address bus width of m...
Definition: rdout_ipb_slave.vhd:30
rdout_ipb_slave.ipb_clk
in ipb_clk std_logic
IPBus Clock input.
Definition: rdout_ipb_slave.vhd:36
rdout_ipb_slave.RAW_FIFO_MAX_ADDR_WIDTH
RAW_FIFO_MAX_ADDR_WIDTH positive := 11
address bus width of merged FIFO RAMs after TOB merging
Definition: rdout_ipb_slave.vhd:26
rdout_ipb_slave.tob_fifo_XOFF_thresh_assert
out tob_fifo_XOFF_thresh_assert std_logic_vector( 15 downto 0)
XOFF FIFO partial full flag thresholds.
Definition: rdout_ipb_slave.vhd:70
rdout_ipb_slave.ipbus_out_built_fifo_wbus_array
out ipbus_out_built_fifo_wbus_array ipb_wbus_array( 1 downto 0)
Aurora output spy RAMs.
Definition: rdout_ipb_slave.vhd:52
rdout_ipb_slave.tob_fifo_prog_full_thresh_assert
out tob_fifo_prog_full_thresh_assert std_logic_vector( 15 downto 0)
BUSY FIFO partial full flag thresholds.
Definition: rdout_ipb_slave.vhd:64
Generated on Tue Nov 11 2025 09:44:32 for eFEX firmware by   doxygen 1.9.1