Behavioral Architecture Reference

Control FPGA data_path slave registers. More...

Processes
update_counter_bcr_block	( clk_320 )
register_update_control	( clk_320 )
register_update	( clk_320 )

Constants
mgt_slv_bus	integer_array ( 7 downto 0 ) := ( N_SLV_RAW_MGT_STATUS_P3 , N_SLV_RAW_MGT_STATUS_P2 , N_SLV_RAW_MGT_STATUS_P1 , N_SLV_RAW_MGT_STATUS_P0 , N_SLV_TOB_MGT_STATUS_P3 , N_SLV_TOB_MGT_STATUS_P2 , N_SLV_TOB_MGT_STATUS_P1 , N_SLV_TOB_MGT_STATUS_P0 )
fifo_slv_bus	integer_array ( 15 downto 0 ) := ( N_SLV_MERGED_FIFO_STATUS_B_DEBUG , N_SLV_MERGED_FIFO_STATUS_B_TOB , N_SLV_MERGED_FIFO_STATUS_A_DEBUG , N_SLV_MERGED_FIFO_STATUS_A_TOB , N_SLV_RAW_FIFO_STATUS_P3 , N_SLV_RAW_FIFO_STATUS_P2 , N_SLV_RAW_FIFO_STATUS_P1 , N_SLV_RAW_FIFO_STATUS_P0 , N_SLV_TOB_FIFO_STATUS_B_P3 , N_SLV_TOB_FIFO_STATUS_B_P2 , N_SLV_TOB_FIFO_STATUS_B_P1 , N_SLV_TOB_FIFO_STATUS_B_P0 , N_SLV_TOB_FIFO_STATUS_A_P3 , N_SLV_TOB_FIFO_STATUS_A_P2 , N_SLV_TOB_FIFO_STATUS_A_P1 , N_SLV_TOB_FIFO_STATUS_A_P0 )
merger_status_slv_bus	integer_array ( 1 downto 0 ) := ( N_SLV_TOB_MERGER_STATUS_B_MERGER , N_SLV_TOB_MERGER_STATUS_A_MERGER )
merger_slv_bus	integer_array ( 7 downto 0 ) := ( N_SLV_TOB_MERGER_STATUS_B_P3 , N_SLV_TOB_MERGER_STATUS_B_P2 , N_SLV_TOB_MERGER_STATUS_B_P1 , N_SLV_TOB_MERGER_STATUS_B_P0 , N_SLV_TOB_MERGER_STATUS_A_P3 , N_SLV_TOB_MERGER_STATUS_A_P2 , N_SLV_TOB_MERGER_STATUS_A_P1 , N_SLV_TOB_MERGER_STATUS_A_P0 )
mux_active_slv_bus	integer_array ( 1 downto 0 ) := ( N_SLV_MUX_STATUS_B_MUX_ACTIVE , N_SLV_MUX_STATUS_A_MUX_ACTIVE )
mux_slv_bus	integer_array ( 11 downto 0 ) := ( N_SLV_MUX_STATUS_B_RAW_3 , N_SLV_MUX_STATUS_B_RAW_2 , N_SLV_MUX_STATUS_B_RAW_1 , N_SLV_MUX_STATUS_B_RAW_0 , N_SLV_MUX_STATUS_B_DEBUG , N_SLV_MUX_STATUS_B_TOB , N_SLV_MUX_STATUS_A_RAW_3 , N_SLV_MUX_STATUS_A_RAW_2 , N_SLV_MUX_STATUS_A_RAW_1 , N_SLV_MUX_STATUS_A_RAW_0 , N_SLV_MUX_STATUS_A_DEBUG , N_SLV_MUX_STATUS_A_TOB )
tob_fifo_default_busy_assert_threshold	std_logic_vector ( 31 downto 0 ) := ( 31 downto TOB_FIFO_MAX_ADDR_WIDTH = > ' 0 ' ) & ( TOB_FIFO_MAX_ADDR_WIDTH- 1 downto PACKET_MAX_WIDTH = > ' 1 ' ) & ( PACKET_MAX_WIDTH - 1 downto 0 = > ' 0 ' )
tob_fifo_default_busy_negate_threshold	std_logic_vector ( 31 downto 0 ) := ( 31 downto TOB_FIFO_MAX_ADDR_WIDTH = > ' 0 ' ) & ( TOB_FIFO_MAX_ADDR_WIDTH- 1 downto PACKET_MAX_WIDTH + 1 = > ' 1 ' ) & ( PACKET_MAX_WIDTH downto 0 = > ' 0 ' )
raw_fifo_default_busy_assert_threshold	std_logic_vector ( 31 downto 0 ) := ( 31 downto RAW_FIFO_MAX_ADDR_WIDTH = > ' 0 ' ) & ( RAW_FIFO_MAX_ADDR_WIDTH - 1 downto PACKET_MAX_WIDTH - 1 = > ' 1 ' ) & ( PACKET_MAX_WIDTH - 2 downto 0 = > ' 0 ' )
raw_fifo_default_busy_negate_threshold	std_logic_vector ( 31 downto 0 ) := ( 31 downto RAW_FIFO_MAX_ADDR_WIDTH = > ' 0 ' ) & ( RAW_FIFO_MAX_ADDR_WIDTH - 1 downto PACKET_MAX_WIDTH = > ' 1 ' ) & ( PACKET_MAX_WIDTH - 1 downto 0 = > ' 0 ' )
tob_fifo_default_assert_threshold	std_logic_vector ( 31 downto 0 ) := ( 31 downto TOB_FIFO_MAX_ADDR_WIDTH = > ' 0 ' ) & ( TOB_FIFO_MAX_ADDR_WIDTH- 1 downto PACKET_MAX_WIDTH + 1 = > ' 1 ' ) & ( PACKET_MAX_WIDTH downto 0 = > ' 0 ' )
tob_fifo_default_negate_threshold	std_logic_vector ( 31 downto 0 ) := ( 31 downto TOB_FIFO_MAX_ADDR_WIDTH = > ' 0 ' ) & ( TOB_FIFO_MAX_ADDR_WIDTH- 1 downto PACKET_MAX_WIDTH + 2 = > ' 1 ' ) & ( PACKET_MAX_WIDTH + 1 downto 0 = > ' 0 ' )
merged_fifo_default_assert_threshold	std_logic_vector ( 31 downto 0 ) := ( 31 downto MERGED_FIFO_MAX_ADDR_WIDTH = > ' 0 ' ) & ( MERGED_FIFO_MAX_ADDR_WIDTH - 1 downto PACKET_MAX_WIDTH + 2 = > ' 1 ' ) & ( PACKET_MAX_WIDTH + 1 downto 0 = > ' 0 ' )
merged_fifo_default_negate_threshold	std_logic_vector ( 31 downto 0 ) := ( 31 downto MERGED_FIFO_MAX_ADDR_WIDTH = > ' 0 ' ) & ( MERGED_FIFO_MAX_ADDR_WIDTH - 1 downto PACKET_MAX_WIDTH + 3 = > ' 1 ' ) & ( PACKET_MAX_WIDTH + 2 downto 0 = > ' 0 ' )
raw_fifo_default_assert_threshold	std_logic_vector ( 31 downto 0 ) := ( 31 downto RAW_FIFO_MAX_ADDR_WIDTH = > ' 0 ' ) & ( RAW_FIFO_MAX_ADDR_WIDTH - 1 downto PACKET_MAX_WIDTH = > ' 1 ' ) & ( PACKET_MAX_WIDTH - 1 downto 0 = > ' 0 ' )
raw_fifo_default_negate_threshold	std_logic_vector ( 31 downto 0 ) := ( 31 downto RAW_FIFO_MAX_ADDR_WIDTH = > ' 0 ' ) & ( RAW_FIFO_MAX_ADDR_WIDTH - 1 downto PACKET_MAX_WIDTH + 1 = > ' 1 ' ) & ( PACKET_MAX_WIDTH downto 0 = > ' 0 ' )

Types
integer_array	array ( natural range <> ) of integer range 0 to N_SLAVES

Signals
ipbw	ipb_wbus_array ( N_SLAVES- 1 downto 0 )
ipbr	ipb_rbus_array ( N_SLAVES- 1 downto 0 )
update_counter_reg_i	std_logic_vector ( 31 downto 0 )
update_counter_reg_1	std_logic
update_counter_reg_2	std_logic
update_counter_reg_3	std_logic
update_counter_bcr	std_logic
update_counter_reg	std_logic
tob_fifo_prog_full_thresh_assert_i	std_logic_vector ( 31 downto 0 )
tob_fifo_prog_full_thresh_negate_i	std_logic_vector ( 31 downto 0 )
raw_fifo_prog_full_thresh_assert_i	std_logic_vector ( 31 downto 0 )
raw_fifo_prog_full_thresh_negate_i	std_logic_vector ( 31 downto 0 )
tob_fifo_xoff_thresh_assert_i	std_logic_vector ( 31 downto 0 )
tob_fifo_xoff_thresh_negate_i	std_logic_vector ( 31 downto 0 )
merged_fifo_xoff_thresh_assert_i	std_logic_vector ( 31 downto 0 )
merged_fifo_xoff_thresh_negate_i	std_logic_vector ( 31 downto 0 )
raw_fifo_xoff_thresh_assert_i	std_logic_vector ( 31 downto 0 )
raw_fifo_xoff_thresh_negate_i	std_logic_vector ( 31 downto 0 )
dbg_fifo_xoff_thresh_assert_i	std_logic_vector ( 31 downto 0 )
dbg_fifo_xoff_thresh_negate_i	std_logic_vector ( 31 downto 0 )
mgt_packet_count_bus	mgt_data_array ( 7 downto 0 )
mgt_safe_mode_count_bus	mgt_data_array ( 7 downto 0 )
mgt_mgt_error_count_bus	mgt_data_array ( 7 downto 0 )
mgt_length_error_count_bus	mgt_data_array ( 7 downto 0 )
mgt_bcn_error_count_bus	mgt_data_array ( 7 downto 0 )
mgt_last_l1id_bus	mgt_data_array ( 7 downto 0 )
mgt_bad_l1id_bus	mgt_data_array ( 7 downto 0 )
fifo_fill_level_bus	fifo_status_array ( 15 downto 0 )
fifo_fill_level_watermark_bus	fifo_status_array ( 15 downto 0 )
fifo_packet_count_bus	fifo_status_array ( 15 downto 0 )
fifo_packet_count_watermark_bus	fifo_status_array ( 15 downto 0 )
fifo_bc_count_i	std_logic_vector ( 31 downto 0 )
fifo_xoff_total_count_bus	mgt_data_array ( 15 downto 0 )
fifo_xoff_last_count_bus	mgt_data_array ( 15 downto 0 )
fifo_xoff_assert_count_bus	mgt_data_array ( 15 downto 0 )
fifo_busy_total_count_bus	mgt_data_array ( 15 downto 0 )
fifo_busy_last_count_bus	mgt_data_array ( 15 downto 0 )
fifo_busy_assert_count_bus	mgt_data_array ( 15 downto 0 )
fifo_error_count_bus	mgt_data_array ( 15 downto 0 )
merger_l1a_count_bus	mgt_data_array ( 1 downto 0 )
merger_last_l1id_bus	mgt_data_array ( 1 downto 0 )
merger_merged_count_bus	mgt_data_array ( 7 downto 0 )
merger_missing_count_bus	mgt_data_array ( 7 downto 0 )
merger_debug_count_bus	mgt_data_array ( 7 downto 0 )
mux_orbit_active_bus_i	fifo_status_array ( 1 downto 0 )
mux_orbit_active_watermark_bus	fifo_status_array ( 1 downto 0 )
mux_packet_active_bus	fifo_status_array ( 11 downto 0 )
mux_packet_active_watermark_bus	fifo_status_array ( 11 downto 0 )
mux_packet_count_bus	mgt_data_array ( 11 downto 0 )
mux_last_l1id_bus	mgt_data_array ( 11 downto 0 )

Instantiations
ipbus_fabric	ipbus_fabric_sel
control_registers	ipbus_ctrlreg_v
mgt_status	ipbus_ctrlreg_v
fifo_status	ipbus_ctrlreg_v
merger_overall_status	ipbus_ctrlreg_v
merger_channel_status	ipbus_ctrlreg_v
mux_orbit_status	ipbus_ctrlreg_v
mux_channel_status	ipbus_ctrlreg_v
fifo_control	ipbus_ctrlreg_v

Detailed Description

Control FPGA data_path slave registers.

This module provides IPBus access for all Read Only and Read/Write registers within the Control FPGA data_path block.

Author

Saeed Taghavi and David Sankey

Definition at line 185 of file rdout_ipb_slave.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/rdout_ipb_slave.vhd