rdout_err_cnt Entity Reference

Control FPGA readout counter registers. More...

Inheritance diagram for rdout_err_cnt:

Entities
Behavioral	architecture
	Control FPGA readout counter registers. More...

Libraries
IEEE
ipbus_lib
infrastructure_lib

Use Clauses
STD_LOGIC_1164
ipbus
packet_mux_type	Package <packet_mux_type>

Ports
clk_320	in	std_logic
rst_320	in	std_logic
rst_err_cntrs	in	std_logic
rst_status_cntrs	in	std_logic
tob_fifo_error_A_bus	in	std_logic_vector ( 3 downto 0 )
tob_fifo_error_B_bus	in	std_logic_vector ( 3 downto 0 )
merged_fifo_error_A_bus	in	std_logic_vector ( 1 downto 0 )
merged_fifo_error_B_bus	in	std_logic_vector ( 1 downto 0 )
raw_fifo_error_bus	in	std_logic_vector ( 3 downto 0 )
tob_mgt_packet_received_bus	in	std_logic_vector ( 3 downto 0 )
tob_mgt_safe_mode_bus	in	std_logic_vector ( 3 downto 0 )
tob_mgt_packet_err_bus	in	std_logic_vector ( 3 downto 0 )
tob_mgt_length_err_bus	in	std_logic_vector ( 3 downto 0 )
tob_mgt_bcn_err_bus	in	std_logic_vector ( 3 downto 0 )
raw_mgt_packet_received_bus	in	std_logic_vector ( 3 downto 0 )
raw_mgt_safe_mode_bus	in	std_logic_vector ( 3 downto 0 )
raw_mgt_packet_err_bus	in	std_logic_vector ( 3 downto 0 )
raw_mgt_length_err_bus	in	std_logic_vector ( 3 downto 0 )
TOB_packet_merged_A_bus	in	std_logic_vector ( 3 downto 0 )
TOB_packet_missing_A_bus	in	std_logic_vector ( 3 downto 0 )
debug_packet_created_A_bus	in	std_logic_vector ( 3 downto 0 )
TOB_packet_merged_B_bus	in	std_logic_vector ( 3 downto 0 )
TOB_packet_missing_B_bus	in	std_logic_vector ( 3 downto 0 )
debug_packet_created_B_bus	in	std_logic_vector ( 3 downto 0 )
L1A_seen_bus	in	std_logic_vector ( 1 downto 0 )
mux_a_pkt_bus	in	std_logic_vector ( 5 downto 0 )
mux_b_pkt_bus	in	std_logic_vector ( 5 downto 0 )
tob_fifo_err_cnt_A_bus_out	out	mgt_data_array ( 3 downto 0 )
tob_fifo_err_cnt_B_bus_out	out	mgt_data_array ( 3 downto 0 )
merged_fifo_err_cnt_A_bus_out	out	mgt_data_array ( 1 downto 0 )
merged_fifo_err_cnt_B_bus_out	out	mgt_data_array ( 1 downto 0 )
raw_fifo_err_cnt_out	out	mgt_data_array ( 3 downto 0 )
tob_mgt_packet_received_cnt_bus_out	out	mgt_data_array ( 3 downto 0 )
tob_mgt_safe_mode_cnt_bus_out	out	mgt_data_array ( 3 downto 0 )
tob_mgt_packet_err_cnt_bus_out	out	mgt_data_array ( 3 downto 0 )
tob_mgt_length_err_cnt_bus_out	out	mgt_data_array ( 3 downto 0 )
tob_mgt_bcn_err_cnt_bus_out	out	mgt_data_array ( 3 downto 0 )
raw_mgt_packet_received_cnt_bus_out	out	mgt_data_array ( 3 downto 0 )
raw_mgt_safe_mode_cnt_bus_out	out	mgt_data_array ( 3 downto 0 )
raw_mgt_packet_err_cnt_bus_out	out	mgt_data_array ( 3 downto 0 )
raw_mgt_length_err_cnt_bus_out	out	mgt_data_array ( 3 downto 0 )
TOB_packet_merged_cnt_A_bus_out	out	mgt_data_array ( 3 downto 0 )
TOB_packet_missing_cnt_A_bus_out	out	mgt_data_array ( 3 downto 0 )
debug_packet_created_cnt_A_bus_out	out	mgt_data_array ( 3 downto 0 )
L1A_cnt_merger_A	out	std_logic_vector ( 31 downto 0 )
TOB_packet_merged_cnt_B_bus_out	out	mgt_data_array ( 3 downto 0 )
TOB_packet_missing_cnt_B_bus_out	out	mgt_data_array ( 3 downto 0 )
debug_packet_created_cnt_B_bus_out	out	mgt_data_array ( 3 downto 0 )
L1A_cnt_merger_B	out	std_logic_vector ( 31 downto 0 )
mux_a_pkt_cnt_bus_out	out	mgt_data_array ( 5 downto 0 )
mux_b_pkt_cnt_bus_out	out	mgt_data_array ( 5 downto 0 )

Detailed Description

Control FPGA readout counter registers.

This module implements all readout counters. FIFO errors are the read & write address clash.

Author

Saeed Taghavi

Definition at line 19 of file rdout_err_cnt.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/rdout_err_cnt.vhd