Behavioral Architecture Reference

Control FPGA readout counter registers. More...

Signals
error_counter_rst_i	std_logic
status_counter_rst_i	std_logic

Instantiations
l1a_cnt_merger_a_block	cntr_generic <Entity cntr_generic>
l1a_cnt_merger_b_block	cntr_generic <Entity cntr_generic>
u2_tob_fifo_error_a	cntr_generic <Entity cntr_generic>
u3_tob_fifo_error_b	cntr_generic <Entity cntr_generic>
u4_raw_fifo_error	cntr_generic <Entity cntr_generic>
u5_merged_fifo_error_a	cntr_generic <Entity cntr_generic>
u6_merged_fifo_error_b	cntr_generic <Entity cntr_generic>
u2_tob_packet_merged_a	cntr_generic <Entity cntr_generic>
u3_tob_packet_missing_a	cntr_generic <Entity cntr_generic>
u4_debug_packet_created_a	cntr_generic <Entity cntr_generic>
u5_tob_packet_merged_b	cntr_generic <Entity cntr_generic>
u6_tob_packet_missing_b	cntr_generic <Entity cntr_generic>
u7_debug_packet_created_b	cntr_generic <Entity cntr_generic>
tob_mgt_packet_received	cntr_generic <Entity cntr_generic>
tob_mgt_safe_mode	cntr_generic <Entity cntr_generic>
tob_mgt_packet_err	cntr_generic <Entity cntr_generic>
tob_mgt_length_err	cntr_generic <Entity cntr_generic>
tob_mgt_bcn_err	cntr_generic <Entity cntr_generic>
raw_mgt_packet_received	cntr_generic <Entity cntr_generic>
raw_mgt_safe_mode	cntr_generic <Entity cntr_generic>
raw_mgt_packet_err	cntr_generic <Entity cntr_generic>
raw_mgt_length_err	cntr_generic <Entity cntr_generic>
mux_a_pkt_cnt	cntr_generic <Entity cntr_generic>
mux_b_pkt_cnt	cntr_generic <Entity cntr_generic>

Detailed Description

Control FPGA readout counter registers.

This module implements all readout counters. FIFO errors are the read & write address clash.

Author

Saeed Taghavi

Definition at line 91 of file rdout_err_cnt.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/rdout_err_cnt.vhd