rdout_err_cnt.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
library ipbus_lib;
use ipbus_lib.ipbus.all;
 
library infrastructure_lib;
use infrastructure_lib.packet_mux_type.all;
 
entity rdout_err_cnt is
  port (
    clk_320 : in std_logic;
    rst_320 : in std_logic;
    rst_err_cntrs           : in std_logic; -- reset all memory error counters
    rst_status_cntrs        : in std_logic; -- reset all packet status counters
 
    tob_fifo_error_A_bus    : in std_logic_vector(3 downto 0);  -- status to be read by IPBus (if rd & wr pointers crash) to be counted.
    tob_fifo_error_B_bus    : in std_logic_vector(3 downto 0);
    merged_fifo_error_A_bus : in std_logic_vector(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1) count errors
    merged_fifo_error_B_bus : in std_logic_vector(1 downto 0); -- merged TOB FIFO (0), debug FIFO (1)
    raw_fifo_error_bus      : in std_logic_vector(3 downto 0);
 
--  TOB MGT status
    tob_mgt_packet_received_bus : in std_logic_vector(3 downto 0);
    tob_mgt_safe_mode_bus       : in std_logic_vector(3 downto 0);
    tob_mgt_packet_err_bus      : in std_logic_vector(3 downto 0);
    tob_mgt_length_err_bus      : in std_logic_vector(3 downto 0);
    tob_mgt_bcn_err_bus         : in std_logic_vector(3 downto 0);
 
--  Raw MGT status
    raw_mgt_packet_received_bus : in std_logic_vector(3 downto 0);
    raw_mgt_safe_mode_bus       : in std_logic_vector(3 downto 0);
    raw_mgt_packet_err_bus      : in std_logic_vector(3 downto 0);
    raw_mgt_length_err_bus      : in std_logic_vector(3 downto 0);
 
--  TOB merging counts per Processor FPGA
    TOB_packet_merged_A_bus         : in std_logic_vector(3 downto 0);
    TOB_packet_missing_A_bus        : in std_logic_vector(3 downto 0);
    debug_packet_created_A_bus      : in std_logic_vector(3 downto 0);
    TOB_packet_merged_B_bus         : in std_logic_vector(3 downto 0);
    TOB_packet_missing_B_bus        : in std_logic_vector(3 downto 0);
    debug_packet_created_B_bus      : in std_logic_vector(3 downto 0);
    L1A_seen_bus                    : in std_logic_vector(1 downto 0);
 
-- MUX counters
    mux_a_pkt_bus                   : in std_logic_vector(5 downto 0);
    mux_b_pkt_bus                   : in std_logic_vector(5 downto 0);
 
    tob_fifo_err_cnt_A_bus_out    : out mgt_data_array(3 downto 0); -- 32-bit error counter
    tob_fifo_err_cnt_B_bus_out    : out mgt_data_array(3 downto 0); -- 32-bit error counter
    merged_fifo_err_cnt_A_bus_out : out mgt_data_array(1 downto 0); -- 32-bit error counter
    merged_fifo_err_cnt_B_bus_out : out mgt_data_array(1 downto 0); -- 32-bit error counter
    raw_fifo_err_cnt_out          : out mgt_data_array(3 downto 0); -- 32-bit error counter
 
    tob_mgt_packet_received_cnt_bus_out : out mgt_data_array(3 downto 0);   -- 32-bit error counter
    tob_mgt_safe_mode_cnt_bus_out   : out mgt_data_array(3 downto 0);   -- 32-bit error counter
    tob_mgt_packet_err_cnt_bus_out  : out mgt_data_array(3 downto 0);   -- 32-bit error counter
    tob_mgt_length_err_cnt_bus_out  : out mgt_data_array(3 downto 0);   -- 32-bit error counter
    tob_mgt_bcn_err_cnt_bus_out     : out mgt_data_array(3 downto 0);   -- 32-bit error counter
 
    raw_mgt_packet_received_cnt_bus_out : out mgt_data_array(3 downto 0);   -- 32-bit error counter
    raw_mgt_safe_mode_cnt_bus_out   : out mgt_data_array(3 downto 0);   -- 32-bit error counter
    raw_mgt_packet_err_cnt_bus_out  : out mgt_data_array(3 downto 0);   -- 32-bit error counter
    raw_mgt_length_err_cnt_bus_out  : out mgt_data_array(3 downto 0);   -- 32-bit error counter
 
    TOB_packet_merged_cnt_A_bus_out     : out mgt_data_array(3 downto 0);   -- 32-bit error counter
    TOB_packet_missing_cnt_A_bus_out    : out mgt_data_array(3 downto 0);   -- 32-bit error counter
    debug_packet_created_cnt_A_bus_out  : out mgt_data_array(3 downto 0);   -- 32-bit error counter
    L1A_cnt_merger_A                    : out std_logic_vector(31 downto 0);
    TOB_packet_merged_cnt_B_bus_out     : out mgt_data_array(3 downto 0);   -- 32-bit error counter
    TOB_packet_missing_cnt_B_bus_out    : out mgt_data_array(3 downto 0);   -- 32-bit error counter
    debug_packet_created_cnt_B_bus_out  : out mgt_data_array(3 downto 0);   -- 32-bit error counter
    L1A_cnt_merger_B                    : out std_logic_vector(31 downto 0);
 
    mux_a_pkt_cnt_bus_out           : out mgt_data_array(5 downto 0);
    mux_b_pkt_cnt_bus_out           : out mgt_data_array(5 downto 0)
 
    );
end rdout_err_cnt;
 
architecture Behavioral of rdout_err_cnt is
 
    signal error_counter_rst_i   : std_logic;
    signal status_counter_rst_i : std_logic;
 
begin
    error_counter_rst_i   <= rst_320 OR rst_err_cntrs;  -- reset all error counters
    status_counter_rst_i <= rst_320 OR rst_status_cntrs;    -- reset all status counters
 
L1A_cnt_merger_A_block : entity infrastructure_lib.cntr_generic
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => L1A_seen_bus(0),  -- if a valid data, then increment the address
      CLK => clk_320,
      RST => error_counter_rst_i,
      Q   => L1A_cnt_merger_A
      );
 
L1A_cnt_merger_B_block : entity infrastructure_lib.cntr_generic
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => L1A_seen_bus(1),  -- if a valid data, then increment the address
      CLK => clk_320,
      RST => error_counter_rst_i,
      Q   => L1A_cnt_merger_B
      );
 
GENERATE_1 : for i in 0 to 3 generate  -- generate for 4
 
  U2_tob_fifo_error_A : entity infrastructure_lib.cntr_generic -- generate for 4 tob_fifo_error_A
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => tob_fifo_error_A_bus(i),  -- if a valid data, then increment the address
      CLK => clk_320,
      RST => error_counter_rst_i,
      Q   => tob_fifo_err_cnt_A_bus_out(i)
      );
 
  U3_tob_fifo_error_B : entity infrastructure_lib.cntr_generic -- generate for 4 tob_fifo_error_B
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => tob_fifo_error_B_bus(i),  -- if a valid data, then increment the address
      CLK => clk_320,
      RST => error_counter_rst_i,
      Q   => tob_fifo_err_cnt_B_bus_out(i)
      );
 
  U4_raw_fifo_error : entity infrastructure_lib.cntr_generic -- generate for 4 raw_fifo_error
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => raw_fifo_error_bus(i),  -- if a valid data, then increment the address
      CLK => clk_320,
      RST => error_counter_rst_i,
      Q   => raw_fifo_err_cnt_out(i)
      );
 
end generate GENERATE_1;
 
GENERATE_2 : for i in 0 to 1 generate  -- generate for 2
 
  U5_merged_fifo_error_A : entity infrastructure_lib.cntr_generic -- generate for 2 merged_fifo_error_A
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => merged_fifo_error_A_bus(i),  -- if a valid data, then increment the address
      CLK => clk_320,
      RST => error_counter_rst_i,
      Q   => merged_fifo_err_cnt_A_bus_out(i)
      );
 
  U6_merged_fifo_error_B : entity infrastructure_lib.cntr_generic -- generate for 2 merged_fifo_error_B
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => merged_fifo_error_B_bus(i),  -- if a valid data, then increment the address
      CLK => clk_320,
      RST => error_counter_rst_i,
      Q   => merged_fifo_err_cnt_B_bus_out(i)
      );
 
end generate GENERATE_2;
 
GENERATE_3 : for i in 0 to 3 generate  -- generate for 4
 
  U2_TOB_packet_merged_A : entity infrastructure_lib.cntr_generic -- generate for packet generation
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => TOB_packet_merged_A_bus(i),  -- if a valid data, then increment the address
      CLK => clk_320,
      RST => status_counter_rst_i,
      Q   => TOB_packet_merged_cnt_A_bus_out(i)
      );
 
  U3_TOB_packet_missing_A : entity infrastructure_lib.cntr_generic -- generate for 4 tob_fifo_error_B
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => TOB_packet_missing_A_bus(i),  -- if a valid data, then increment the address
      CLK => clk_320,
      RST => status_counter_rst_i,
      Q   => TOB_packet_missing_cnt_A_bus_out(i)
      );
 
  U4_debug_packet_created_A : entity infrastructure_lib.cntr_generic -- generate for 4 raw_fifo_error
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => debug_packet_created_A_bus(i),  -- if a valid data, then increment the address
      CLK => clk_320,
      RST => status_counter_rst_i,
      Q   => debug_packet_created_cnt_A_bus_out(i)
      );
 
  U5_TOB_packet_merged_B : entity infrastructure_lib.cntr_generic -- generate for 4 tob_fifo_error_A
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => TOB_packet_merged_B_bus(i),  -- if a valid data, then increment the address
      CLK => clk_320,
      RST => status_counter_rst_i,
      Q   => TOB_packet_merged_cnt_B_bus_out(i)
      );
 
  U6_TOB_packet_missing_B : entity infrastructure_lib.cntr_generic -- generate for 4 tob_fifo_error_B
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => TOB_packet_missing_B_bus(i),  -- if a valid data, then increment the address
      CLK => clk_320,
      RST => status_counter_rst_i,
      Q   => TOB_packet_missing_cnt_B_bus_out(i)
      );
 
  U7_debug_packet_created_B : entity infrastructure_lib.cntr_generic -- generate for 4 raw_fifo_error
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => debug_packet_created_B_bus(i),  -- if a valid data, then increment the address
      CLK => clk_320,
      RST => status_counter_rst_i,
      Q   => debug_packet_created_cnt_B_bus_out(i)
      );
 
end generate GENERATE_3;
 
GENERATE_4 : for i in 0 to 3 generate  -- generate for 4
 
  tob_mgt_packet_received : entity infrastructure_lib.cntr_generic
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => tob_mgt_packet_received_bus(i),
      CLK => clk_320,
      RST => status_counter_rst_i,
      Q   => tob_mgt_packet_received_cnt_bus_out(i));
 
  tob_mgt_safe_mode : entity infrastructure_lib.cntr_generic
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => tob_mgt_safe_mode_bus(i),
      CLK => clk_320,
      RST => status_counter_rst_i,
      Q   => tob_mgt_safe_mode_cnt_bus_out(i));
 
  tob_mgt_packet_err : entity infrastructure_lib.cntr_generic
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => tob_mgt_packet_err_bus(i),
      CLK => clk_320,
      RST => status_counter_rst_i,
      Q   => tob_mgt_packet_err_cnt_bus_out(i));
 
  tob_mgt_length_err : entity infrastructure_lib.cntr_generic
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => tob_mgt_length_err_bus(i),
      CLK => clk_320,
      RST => status_counter_rst_i,
      Q   => tob_mgt_length_err_cnt_bus_out(i));
 
  tob_mgt_bcn_err : entity infrastructure_lib.cntr_generic
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => tob_mgt_bcn_err_bus(i),
      CLK => clk_320,
      RST => status_counter_rst_i,
      Q   => tob_mgt_bcn_err_cnt_bus_out(i));
 
  raw_mgt_packet_received : entity infrastructure_lib.cntr_generic
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => raw_mgt_packet_received_bus(i),
      CLK => clk_320,
      RST => status_counter_rst_i,
      Q   => raw_mgt_packet_received_cnt_bus_out(i));
 
  raw_mgt_safe_mode : entity infrastructure_lib.cntr_generic
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => raw_mgt_safe_mode_bus(i),
      CLK => clk_320,
      RST => status_counter_rst_i,
      Q   => raw_mgt_safe_mode_cnt_bus_out(i));
 
  raw_mgt_packet_err : entity infrastructure_lib.cntr_generic
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => raw_mgt_packet_err_bus(i),
      CLK => clk_320,
      RST => status_counter_rst_i,
      Q   => raw_mgt_packet_err_cnt_bus_out(i));
 
  raw_mgt_length_err : entity infrastructure_lib.cntr_generic
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => raw_mgt_length_err_bus(i),
      CLK => clk_320,
      RST => status_counter_rst_i,
      Q   => raw_mgt_length_err_cnt_bus_out(i));
 
end generate GENERATE_4;
 
GENERATE_5 : for i in 0 to 5 generate  -- generate for 6
 
  mux_a_pkt_cnt : entity infrastructure_lib.cntr_generic
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => mux_a_pkt_bus(i),
      CLK => clk_320,
      RST => status_counter_rst_i,
      Q   => mux_a_pkt_cnt_bus_out(i));
 
  mux_b_pkt_cnt : entity infrastructure_lib.cntr_generic
    generic map (width => 32, WRAPAROUND => False)
    port map (
      CE  => mux_b_pkt_bus(i),
      CLK => clk_320,
      RST => status_counter_rst_i,
      Q   => mux_b_pkt_cnt_bus_out(i));
 
end generate GENERATE_5;
 
end Behavioral;